Messages in this thread | | | Date | Mon, 9 May 2016 16:29:08 -0700 | From | Stephen Boyd <> | Subject | Re: [PATCH v2] clk: ingenic: Allow divider value to be divided |
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On 05/09, Harvey Hunt wrote: > The JZ4780's MSC clock divider registers multiply the clock divider by 2. > This means that MMC devices run at half their expected speed. Add the > ability to divide the clock divider in order to solve this. > > Signed-off-by: Harvey Hunt <harvey.hunt@imgtec.com> > > Cc: Paul Burton <paul.burton@imgtec.com> > Cc: Ralf Baechle <ralf@linux-mips.org> > Cc: linux-clk@vger.kernel.org > Cc: linux-kernel@vger.kernel.org > ---
Applied to clk-next
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