Messages in this thread | | | Date | Wed, 25 May 2016 10:35:36 +0530 | From | Gautham R Shenoy <> | Subject | Re: [PATCH v4 08/10] powerpc/powernv: Add platform support for stop instruction |
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Hi Shreyas,
On Tue, May 24, 2016 at 06:45:12PM +0530, Shreyas B. Prabhu wrote: > POWER ISA v3 defines a new idle processor core mechanism. In summary, > a) new instruction named stop is added. This instruction replaces > instructions like nap, sleep, rvwinkle. > b) new per thread SPR named Processor Stop Status and Control Register > (PSSCR) is added which controls the behavior of stop instruction. > > PSSCR layout: > ---------------------------------------------------------- > | PLS | /// | SD | ESL | EC | PSLL | /// | TR | MTL | RL | > ---------------------------------------------------------- > 0 4 41 42 43 44 48 54 56 60 > > PSSCR key fields: > Bits 0:3 - Power-Saving Level Status. This field indicates the lowest > power-saving state the thread entered since stop instruction was last > executed. > > Bit 42 - Enable State Loss > 0 - No state is lost irrespective of other fields > 1 - Allows state loss > > Bits 44:47 - Power-Saving Level Limit > This limits the power-saving level that can be entered into. > > Bits 60:63 - Requested Level > Used to specify which power-saving level must be entered on executing > stop instruction > > This patch adds support for stop instruction and PSSCR handling.
This version looks good to me.
Reviewed-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
-- Thanks and Regards gautham.
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