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    Subject[PATCH 3.13.y-ckt 75/97] clk: xgene: Add missing parenthesis when clearing divider value
    Date
    3.13.11-ckt38 -stable review patch.  If anyone has any objections, please let me know.

    ---8<------------------------------------------------------------

    From: Loc Ho <lho@apm.com>

    commit 0f4c7a138dfefb0ebdbaf56e3ba2acd2958a6605 upstream.

    In the initial fix for non-zero divider shift value, the parenthesis
    was missing after the negate operation. This patch adds the required
    parenthesis. Otherwise, lower bits may be cleared unintentionally.

    Signed-off-by: Loc Ho <lho@apm.com>
    Acked-by: Toan Le <toanle@apm.com>
    Fixes: 1382ea631ddd ("clk: xgene: Fix divider with non-zero shift value")
    Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
    Signed-off-by: Kamal Mostafa <kamal@canonical.com>
    ---
    drivers/clk/clk-xgene.c | 4 ++--
    1 file changed, 2 insertions(+), 2 deletions(-)

    diff --git a/drivers/clk/clk-xgene.c b/drivers/clk/clk-xgene.c
    index 1ec5fe8..d9421f8 100644
    --- a/drivers/clk/clk-xgene.c
    +++ b/drivers/clk/clk-xgene.c
    @@ -351,8 +351,8 @@ static int xgene_clk_set_rate(struct clk_hw *hw, unsigned long rate,
    /* Set new divider */
    data = xgene_clk_read(pclk->param.divider_reg +
    pclk->param.reg_divider_offset);
    - data &= ~((1 << pclk->param.reg_divider_width) - 1)
    - << pclk->param.reg_divider_shift;
    + data &= ~(((1 << pclk->param.reg_divider_width) - 1)
    + << pclk->param.reg_divider_shift);
    data |= divider;
    xgene_clk_write(data, pclk->param.divider_reg +
    pclk->param.reg_divider_offset);
    --
    2.7.4
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