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    Subject[RFC PATCH v1 04/18] x86: Add the Secure Memory Encryption cpu feature
    Date
    Update the cpu features to include identifying and reporting on the
    Secure Memory Encryption feature.

    Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
    ---
    arch/x86/include/asm/cpufeature.h | 1 +
    arch/x86/include/asm/cpufeatures.h | 5 ++++-
    arch/x86/kernel/cpu/scattered.c | 1 +
    3 files changed, 6 insertions(+), 1 deletion(-)

    diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
    index 07c942d..e27e352 100644
    --- a/arch/x86/include/asm/cpufeature.h
    +++ b/arch/x86/include/asm/cpufeature.h
    @@ -27,6 +27,7 @@ enum cpuid_leafs
    CPUID_6_EAX,
    CPUID_8000_000A_EDX,
    CPUID_7_ECX,
    + CPUID_8000_001F_EAX,
    };

    #ifdef CONFIG_X86_FEATURE_NAMES
    diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
    index 47b5056..4aea205 100644
    --- a/arch/x86/include/asm/cpufeatures.h
    +++ b/arch/x86/include/asm/cpufeatures.h
    @@ -12,7 +12,7 @@
    /*
    * Defines x86 CPU feature bits
    */
    -#define NCAPINTS 17 /* N 32-bit words worth of info */
    +#define NCAPINTS 18 /* N 32-bit words worth of info */
    #define NBUGINTS 1 /* N 32-bit bug flags */

    /*
    @@ -282,6 +282,9 @@
    #define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */
    #define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */

    +/* AMD SME Feature Identification, CPUID level 0x8000001f (eax), word 17 */
    +#define X86_FEATURE_SME (17*32+ 0) /* Secure Memory Encryption support */
    +
    /*
    * BUG word(s)
    */
    diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
    index 8cb57df..d86d9a5 100644
    --- a/arch/x86/kernel/cpu/scattered.c
    +++ b/arch/x86/kernel/cpu/scattered.c
    @@ -37,6 +37,7 @@ void init_scattered_cpuid_features(struct cpuinfo_x86 *c)
    { X86_FEATURE_HW_PSTATE, CR_EDX, 7, 0x80000007, 0 },
    { X86_FEATURE_CPB, CR_EDX, 9, 0x80000007, 0 },
    { X86_FEATURE_PROC_FEEDBACK, CR_EDX,11, 0x80000007, 0 },
    + { X86_FEATURE_SME, CR_EAX, 0, 0x8000001f, 0 },
    { 0, 0, 0, 0, 0 }
    };

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