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    Subject[PATCH 4.5 207/238] clk: rockchip: rk3368: fix hdmi_cec gate-register
    Date
    4.5-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Heiko Stuebner <heiko@sntech.de>

    commit fd0c0740fac17a014704ef89d8c8b1768711ca59 upstream.

    Fix a typo making the sclk_hdmi_cec access a wrong register to handle
    its gate.

    Fixes: 3536c97a52db ("clk: rockchip: add rk3368 clock controller")
    Signed-off-by: Heiko Stuebner <heiko@sntech.de>
    Reviewed-by: zhangqing <zhangqing@rock-chips.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

    ---
    drivers/clk/rockchip/clk-rk3368.c | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    --- a/drivers/clk/rockchip/clk-rk3368.c
    +++ b/drivers/clk/rockchip/clk-rk3368.c
    @@ -442,7 +442,7 @@ static struct rockchip_clk_branch rk3368
    GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0,
    RK3368_CLKGATE_CON(4), 13, GFLAGS),
    GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 0,
    - RK3368_CLKGATE_CON(5), 12, GFLAGS),
    + RK3368_CLKGATE_CON(4), 12, GFLAGS),

    COMPOSITE_NODIV(0, "vip_src", mux_pll_src_cpll_gpll_p, 0,
    RK3368_CLKSEL_CON(21), 15, 1, MFLAGS,

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