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    Subject[tip:perf/core] perf/x86/intel: Add definition for PT PMI bit
    Commit-ID:  5690ae28e472d25e330ad0c637a5cea3fc39fb32
    Gitweb: http://git.kernel.org/tip/5690ae28e472d25e330ad0c637a5cea3fc39fb32
    Author: Stephane Eranian <eranian@google.com>
    AuthorDate: Thu, 3 Mar 2016 20:50:40 +0100
    Committer: Ingo Molnar <mingo@kernel.org>
    CommitDate: Tue, 8 Mar 2016 12:18:34 +0100

    perf/x86/intel: Add definition for PT PMI bit

    This patch adds a definition for GLOBAL_OVFL_STATUS bit 55
    which is used with the Processor Trace (PT) feature.

    Signed-off-by: Stephane Eranian <eranian@google.com>
    Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
    Cc: <stable@vger.kernel.org>
    Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
    Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
    Cc: Jiri Olsa <jolsa@redhat.com>
    Cc: Linus Torvalds <torvalds@linux-foundation.org>
    Cc: Peter Zijlstra <peterz@infradead.org>
    Cc: Thomas Gleixner <tglx@linutronix.de>
    Cc: Vince Weaver <vincent.weaver@maine.edu>
    Cc: adrian.hunter@intel.com
    Cc: kan.liang@intel.com
    Cc: namhyung@kernel.org
    Link: http://lkml.kernel.org/r/1457034642-21837-2-git-send-email-eranian@google.com
    Signed-off-by: Ingo Molnar <mingo@kernel.org>
    ---
    arch/x86/include/asm/perf_event.h | 1 +
    1 file changed, 1 insertion(+)

    diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
    index 7bcb861..5a2ed3e 100644
    --- a/arch/x86/include/asm/perf_event.h
    +++ b/arch/x86/include/asm/perf_event.h
    @@ -165,6 +165,7 @@ struct x86_pmu_capability {
    #define GLOBAL_STATUS_ASIF BIT_ULL(60)
    #define GLOBAL_STATUS_COUNTERS_FROZEN BIT_ULL(59)
    #define GLOBAL_STATUS_LBRS_FROZEN BIT_ULL(58)
    +#define GLOBAL_STATUS_TRACE_TOPAPMI BIT_ULL(55)

    /*
    * IBS cpuid feature detection
    \
     
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