Messages in this thread | | | Date | Mon, 7 Mar 2016 09:50:21 +0000 | From | Marc Zyngier <> | Subject | Re: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller support |
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On Mon, 7 Mar 2016 11:36:22 +0800 Minghuan Lian <Minghuan.Lian@nxp.com> wrote:
> Some kind of NXP Layerscape SoC provides a MSI > implementation which uses two SCFG registers MSIIR and > MSIR to support 32 MSI interrupts for each PCIe controller. > The patch is to support it. > > Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
The DT binding still needs an Ack from the DT maintainers though (cc'd).
M. -- Jazz is not dead. It just smells funny.
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