Messages in this thread | | | Date | Mon, 21 Mar 2016 11:46:19 +0800 | From | Huang Rui <> | Subject | Re: [PATCH 2/3] x86/topology: Fix AMD core count |
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On Mon, Mar 21, 2016 at 11:07:44AM +0800, Huang Rui wrote: > On Fri, Mar 18, 2016 at 05:41:01PM +0100, Borislav Petkov wrote: > > On Fri, Mar 18, 2016 at 04:03:47PM +0100, Peter Zijlstra wrote: > > > It turns out AMD gets x86_max_cores wrong when there are compute > > > units. > > > > > > The issue is that Linux assumes: > > > > > > nr_logical_cpus = nr_cores * nr_siblings > > > > > > But AMD reports its CU unit as 2 cores, but then sets num_smp_siblings > > > to 2 as well. > > > > > > Cc: Ingo Molnar <mingo@kernel.org> > > > Cc: Borislav Petkov <bp@alien8.de> > > > Cc: Thomas Gleixner <tglx@linutronix.de> > > > Cc: Andreas Herrmann <aherrmann@suse.com> > > > Reported-by: Xiong Zhou <jencce.kernel@gmail.com> > > > Fixes: 1f12e32f4cd5 ("x86/topology: Create logical package id") > > > Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> > > > Link: http://lkml.kernel.org/r/20160317095220.GO6344@twins.programming.kicks-ass.net > > > --- > > > arch/x86/kernel/cpu/amd.c | 8 ++++---- > > > arch/x86/kernel/smpboot.c | 11 ++++++----- > > > 2 files changed, 10 insertions(+), 9 deletions(-) > > > > > > --- a/arch/x86/kernel/cpu/amd.c > > > +++ b/arch/x86/kernel/cpu/amd.c > > > @@ -313,9 +313,9 @@ static void amd_get_topology(struct cpui > > > node_id = ecx & 7; > > > > > > /* get compute unit information */ > > > - smp_num_siblings = ((ebx >> 8) & 3) + 1; > > > + cores_per_cu = smp_num_siblings = ((ebx >> 8) & 3) + 1; > > > + c->x86_max_cores /= smp_num_siblings; > > > c->compute_unit_id = ebx & 0xff; > > > - cores_per_cu += ((ebx >> 8) & 3); > > > } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { > > > u64 value; > > > > > > @@ -331,8 +331,8 @@ static void amd_get_topology(struct cpui > > > u32 cus_per_node; > > > > > > set_cpu_cap(c, X86_FEATURE_AMD_DCM); > > > - cores_per_node = c->x86_max_cores / nodes_per_socket; > > > - cus_per_node = cores_per_node / cores_per_cu; > > > + cus_per_node = c->x86_max_cores / nodes_per_socket; > > > + cores_per_node = cus_per_node * cores_per_cu; > > > > > > /* store NodeID, use llc_shared_map to store sibling info */ > > > per_cpu(cpu_llc_id, cpu) = node_id; > > > > Looks ok to me, however it probably would be prudent if AMD tested it on > > a bunch of machines just to make sure we don't break anything else. I'm > > thinking F15h and F16h, something big... > > > > Rui, can you find some time to run this one please? > > > > Look at before/after info in /proc/cpuinfo, topology in sysfs and dmesg > > before and after might be useful too. > > > > OK, we will find some fam15h, fam16h platforms to verify it. Please > wait for my feedback. > > But I am confused with c->x86_max_cores /= smp_num_siblings, what is > the real meaning of c->x86_max_cores here for AMD, the whole compute > unit numbers per socket? > > + Sherry, for her awareness. >
I quickly applied this patch on tip/master with on a fam15h machine. The issue is still existed, only one core can be detected.
processor : 0 vendor_id : AuthenticAMD cpu family : 21 model : 2 model name : AMD Opteron(tm) Processor 6386 SE stepping : 0 microcode : 0x6000822 cpu MHz : 2792.882 cache size : 2048 KB fpu : yes fpu_exception : yes cpuid level : 13 wp : yes flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc extd_apicid aperfmperf eagerfpu pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 popcnt aes xsave avx f16c lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs xop skinit wdt lwp fma4 tce nodeid_msr tbm topoext perfctr_core perfctr_nb cpb hw_pstate vmmcall bmi1 arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold bugs : fxsave_leak sysret_ss_attrs bogomips : 5585.76 TLB size : 1536 4K pages clflush size : 64 cache_alignment : 64 address sizes : 48 bits physical, 48 bits virtual power management: ts ttp tm 100mhzsteps hwpstate cpb eff_freq_ro
Architecture: x86_64 CPU op-mode(s): 32-bit, 64-bit Byte Order: Little Endian CPU(s): 1 On-line CPU(s) list: 0 Thread(s) per core: 1 Core(s) per socket: 1 Socket(s): 1 Vendor ID: AuthenticAMD CPU family: 21 Model: 2 Stepping: 0 CPU MHz: 2792.882 BogoMIPS: 5585.76 Virtualization: AMD-V L1d cache: 16K L1i cache: 64K L2 cache: 2048K L3 cache: 6144K
Thanks, Rui
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