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SubjectRe: 4.5.0+ panic when setup loop device
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On Thu, 2016-03-17 at 10:52 +0100, Peter Zijlstra wrote:

> Andreas; Borislav said to Cc you since you wrote all this.
> The issue is that Linux assumes:
>
> > nr_logical_cpus = nr_cores * nr_siblings

It also seems to now assume that if SMT is possible, it's enabled.

Below is my 8 socket DL980 G7, which has SMT turned off for RT testing,
booting NOPREEMPT master tuned for maximum bloat ala distro and getting
confused by me telling it (as always) nr_cpus=64. Bad juju ensues.

[ 0.216180] max_cores: 8, cpu_ids: 64, num_siblings: 2, coreid_bits: 5
[ 0.226593] smpboot: Max logical packages: 4 <== not
[ 0.233742] smpboot: APIC(0) Converting physical 0 to logical package 0
[ 0.244233] smpboot: APIC(20) Converting physical 1 to logical package 1
[ 0.253765] smpboot: APIC(40) Converting physical 2 to logical package 2
[ 0.264081] smpboot: APIC(60) Converting physical 3 to logical package 3
[ 0.274827] smpboot: APIC(80) Package 4 exceeds logical package map
[ 0.284705] smpboot: CPU 32 APICId 80 disabled
[ 0.292277] smpboot: APIC(a0) Package 5 exceeds logical package map
[ 0.302141] smpboot: CPU 40 APICId a0 disabled
[ 0.308607] smpboot: APIC(c0) Package 6 exceeds logical package map
[ 0.321682] smpboot: CPU 48 APICId c0 disabled
[ 0.328179] smpboot: APIC(e0) Package 7 exceeds logical package map
[ 0.337902] smpboot: CPU 56 APICId e0 disabled
[ 0.345695] DMAR: Host address width 40
[ 0.351511] DMAR: DRHD base: 0x000000b0100000 flags: 0x0
[ 0.360018] DMAR: dmar0: reg_base_addr b0100000 ver 1:0 cap c90780106f0462 ecap f0207e
[ 0.373342] DMAR: DRHD base: 0x000000a8000000 flags: 0x1
[ 0.383164] DMAR: dmar1: reg_base_addr a8000000 ver 1:0 cap c90780106f0462 ecap f0207e
[ 0.396475] DMAR: RMRR base: 0x0000007f7ee000 end: 0x0000007f7effff
[ 0.407255] DMAR: RMRR base: 0x0000007f7e7000 end: 0x0000007f7ecfff
[ 0.418136] DMAR: RMRR base: 0x0000007f62e000 end: 0x0000007f62ffff
[ 0.429787] DMAR: ATSR flags: 0x0
[ 0.434778] DMAR: ATSR flags: 0x0
[ 0.441624] DMAR-IR: IOAPIC id 10 under DRHD base 0xb0100000 IOMMU 0
[ 0.452716] DMAR-IR: IOAPIC id 8 under DRHD base 0xa8000000 IOMMU 1
[ 0.465782] DMAR-IR: IOAPIC id 0 under DRHD base 0xa8000000 IOMMU 1
[ 0.477123] DMAR-IR: Queued invalidation will be enabled to support x2apic and Intr-remapping.
[ 0.492918] DMAR-IR: Enabled IRQ remapping in x2apic mode
[ 0.502549] x2apic enabled
[ 0.506678] Switched APIC routing to cluster x2apic.
[ 0.519955] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
[ 0.642858] smpboot: CPU0: Intel(R) Xeon(R) CPU X7560 @ 2.27GHz (family: 0x6, model: 0x2e, stepping: 0x6)
[ 0.668111] Performance Events: PEBS fmt1+, 16-deep LBR, Nehalem events, Broken BIOS detected, complain to your hardware vendor.
[ 0.694907] [Firmware Bug]: the BIOS has corrupted hw-PMU resources (MSR 38d is 330)
[ 0.713186] Intel PMU driver.
[ 0.719091] core: CPU erratum AAJ80 worked around
[ 0.731647] core: CPUID marked event: 'bus cycles' unavailable
[ 0.741499] ... version: 3
[ 0.747982] ... bit width: 48
[ 0.754109] ... generic registers: 4
[ 0.760980] ... value mask: 0000ffffffffffff
[ 0.769336] ... max period: 000000007fffffff
[ 0.776913] ... fixed-purpose events: 3
[ 0.783861] ... event mask: 000000070000000f
[ 0.793737] x86: Booting SMP configuration:
[ 0.800069] .... node #0, CPUs: #1 #2 #3 #4 #5 #6 #7 #8 #9 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #33 #34 #35 #36 #37 #38 #39 #41 #42 #43 #44 #45 #46 #47 #49 #50 #51 #5>
[ 4.717309] x86: Booted up 1 node, 60 CPUs
[ 4.724551] smpboot: Total of 60 processors activated (271280.00 BogoMIPS)
[ 5.007438] node 0 initialised, 1013474 pages in 36ms

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