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    Subject[PATCH 3.19.y-ckt 53/70] ARM: dts: dra7: do not gate cpsw clock due to errata i877
    Date
    v3.19.8-ckt17 -stable review patch.  If anyone has any objections, please let me know.

    ---8<------------------------------------------------------------

    From: Mugunthan V N <mugunthanvnm@ti.com>

    commit 0f514e690740e54815441a87708c3326f8aa8709 upstream.

    Errata id: i877

    Description:
    ------------
    The RGMII 1000 Mbps Transmit timing is based on the output clock
    (rgmiin_txc) being driven relative to the rising edge of an internal
    clock and the output control/data (rgmiin_txctl/txd) being driven relative
    to the falling edge of an internal clock source. If the internal clock
    source is allowed to be static low (i.e., disabled) for an extended period
    of time then when the clock is actually enabled the timing delta between
    the rising edge and falling edge can change over the lifetime of the
    device. This can result in the device switching characteristics degrading
    over time, and eventually failing to meet the Data Manual Delay Time/Skew
    specs.
    To maintain RGMII 1000 Mbps IO Timings, SW should minimize the
    duration that the Ethernet internal clock source is disabled. Note that
    the device reset state for the Ethernet clock is "disabled".
    Other RGMII modes (10 Mbps, 100Mbps) are not affected

    Workaround:
    -----------
    If the SoC Ethernet interface(s) are used in RGMII mode at 1000 Mbps,
    SW should minimize the time the Ethernet internal clock source is disabled
    to a maximum of 200 hours in a device life cycle. This is done by enabling
    the clock as early as possible in IPL (QNX) or SPL/u-boot (Linux/Android)
    by setting the register CM_GMAC_CLKSTCTRL[1:0]CLKTRCTRL = 0x2:SW_WKUP.

    So, do not allow to gate the cpsw clocks using ti,no-idle property in
    cpsw node assuming 1000 Mbps is being used all the time. If someone does
    not need 1000 Mbps and wants to gate clocks to cpsw, this property needs
    to be deleted in their respective board files.

    Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
    Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
    Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
    Signed-off-by: Paul Walmsley <paul@pwsan.com>
    Signed-off-by: Kamal Mostafa <kamal@canonical.com>
    ---
    arch/arm/boot/dts/dra7.dtsi | 10 ++++++++++
    1 file changed, 10 insertions(+)

    diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
    index 63f8b00..e26a0e6 100644
    --- a/arch/arm/boot/dts/dra7.dtsi
    +++ b/arch/arm/boot/dts/dra7.dtsi
    @@ -1369,6 +1369,16 @@
    0x48485200 0x2E00>;
    #address-cells = <1>;
    #size-cells = <1>;
    +
    + /*
    + * Do not allow gating of cpsw clock as workaround
    + * for errata i877. Keeping internal clock disabled
    + * causes the device switching characteristics
    + * to degrade over time and eventually fail to meet
    + * the data manual delay time/skew specs.
    + */
    + ti,no-idle;
    +
    /*
    * rx_thresh_pend
    * rx_pend
    --
    2.7.0
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