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SubjectRe: [PATCH v2 1/2] iommu/io-pgtable: Add MTK 4GB mode in Short-descriptor
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On 13/03/16 22:01, Yong Wu wrote:
> In MT8173, Normally the first 1GB PA is for the HW SRAM and Regs,
> so the PA will be 33bits if the dram size is 4GB. We have a
> "DRAM 4GB mode" toggle bit for this. If it's enabled, from CPU's
> point of view, the dram PA will be from 0x1_00000000~0x1_ffffffff.
>
> In short descriptor, the pagetable descriptor is always 32bit.
> Mediatek extend bit9 in the lvl1 and lvl2 pgtable descriptor
> as the 4GB mode.
>
> In the 4GB mode, the bit9 must be set, then M4U help add 0x1_00000000
> based on the PA in pagetable. Thus the M4U output address to EMI is
> always 33bits(the input address is still 32bits).
>
> We add a special quirk for this MTK-4GB mode. And in the standard
> spec, Bit9 in the lvl1 is "IMPLEMENTATION DEFINED", while it's AP[2]
> in the lvl2, therefore if this quirk is enabled, NO_PERMS is also
> expected.

Cool, thanks for making it make sense.

> Signed-off-by: Yong Wu <yong.wu@mediatek.com>

I guess there's some other hardware magic that deals with the address in
the TTBR being truncated to 32 bits, but for this code doing what it
claims to do:

Reviewed-by: Robin Murphy <robin.murphy@arm.com>

> ---
> drivers/iommu/io-pgtable-arm-v7s.c | 13 ++++++++++++-
> drivers/iommu/io-pgtable.h | 6 ++++++
> 2 files changed, 18 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c
> index 9fcceb1..32b371b 100644
> --- a/drivers/iommu/io-pgtable-arm-v7s.c
> +++ b/drivers/iommu/io-pgtable-arm-v7s.c
> @@ -121,6 +121,8 @@
> #define ARM_V7S_TEX_MASK 0x7
> #define ARM_V7S_ATTR_TEX(val) (((val) & ARM_V7S_TEX_MASK) << ARM_V7S_TEX_SHIFT)
>
> +#define ARM_V7S_ATTR_MTK_4GB BIT(9) /* MTK extend it for 4GB mode */
> +
> /* *well, except for TEX on level 2 large pages, of course :( */
> #define ARM_V7S_CONT_PAGE_TEX_SHIFT 6
> #define ARM_V7S_CONT_PAGE_TEX_MASK (ARM_V7S_TEX_MASK << ARM_V7S_CONT_PAGE_TEX_SHIFT)
> @@ -364,6 +366,9 @@ static int arm_v7s_init_pte(struct arm_v7s_io_pgtable *data,
> if (lvl == 1 && (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS))
> pte |= ARM_V7S_ATTR_NS_SECTION;
>
> + if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB)
> + pte |= ARM_V7S_ATTR_MTK_4GB;
> +
> if (num_entries > 1)
> pte = arm_v7s_pte_to_cont(pte, lvl);
>
> @@ -625,9 +630,15 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
>
> if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS |
> IO_PGTABLE_QUIRK_NO_PERMS |
> - IO_PGTABLE_QUIRK_TLBI_ON_MAP))
> + IO_PGTABLE_QUIRK_TLBI_ON_MAP |
> + IO_PGTABLE_QUIRK_ARM_MTK_4GB))
> return NULL;
>
> + /* If ARM_MTK_4GB is enabled, the NO_PERMS is also expected. */
> + if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB &&
> + !(cfg->quirks & IO_PGTABLE_QUIRK_NO_PERMS))
> + return NULL;
> +
> data = kmalloc(sizeof(*data), GFP_KERNEL);
> if (!data)
> return NULL;
> diff --git a/drivers/iommu/io-pgtable.h b/drivers/iommu/io-pgtable.h
> index d4f5027..969d82c 100644
> --- a/drivers/iommu/io-pgtable.h
> +++ b/drivers/iommu/io-pgtable.h
> @@ -60,10 +60,16 @@ struct io_pgtable_cfg {
> * IO_PGTABLE_QUIRK_TLBI_ON_MAP: If the format forbids caching invalid
> * (unmapped) entries but the hardware might do so anyway, perform
> * TLB maintenance when mapping as well as when unmapping.
> + *
> + * IO_PGTABLE_QUIRK_ARM_MTK_4GB: (ARM v7s format) Set bit 9 in all
> + * PTEs, for Mediatek IOMMUs which treat it as a 33rd address bit
> + * when the SoC is in "4GB mode" and they can only access the high
> + * remap of DRAM (0x1_00000000 to 0x1_ffffffff).
> */
> #define IO_PGTABLE_QUIRK_ARM_NS BIT(0)
> #define IO_PGTABLE_QUIRK_NO_PERMS BIT(1)
> #define IO_PGTABLE_QUIRK_TLBI_ON_MAP BIT(2)
> + #define IO_PGTABLE_QUIRK_ARM_MTK_4GB BIT(3)
> unsigned long quirks;
> unsigned long pgsize_bitmap;
> unsigned int ias;
>

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