Messages in this thread | | | From | Arnd Bergmann <> | Subject | Re: [RFC PATCH v2 1/3] PCI: hisi: re-architect Hip05/Hip06 controllers driver to preapare for ACPI | Date | Mon, 08 Feb 2016 17:32:48 +0100 |
| |
On Monday 08 February 2016 16:06:54 Gabriele Paoloni wrote: > > > > On Monday 08 February 2016 12:41:02 Gabriele Paoloni wrote: > > > + > > > +/* HipXX PCIe host only supports 32-bit config access */ > > > +int hisi_pcie_common_cfg_read(void __iomem *reg_base, int where, int > > size, > > > + u32 *val) > > > +{ > > > + u32 reg; > > > + u32 reg_val; > > > + void *walker = ®_val; > > > + > > > + walker += (where & 0x3); > > > + reg = where & ~0x3; > > > + reg_val = readl(reg_base + reg); > > > + > > > + if (size == 1) > > > + *val = *(u8 __force *) walker; > > > + else if (size == 2) > > > + *val = *(u16 __force *) walker; > > > + else if (size == 4) > > > + *val = reg_val; > > > + else > > > + return PCIBIOS_BAD_REGISTER_NUMBER; > > > + > > > + return PCIBIOS_SUCCESSFUL; > > > +} > > > > Isn't this the same hack that Qualcomm are using? > > As far as I can see Qualcomm defines its own config access > mechanism only for RC config read and also it seems they're > having problems with reporting the device class... > > https://github.com/torvalds/linux/blob/master/drivers/pci/host/pcie-qcom.c#L474 > > Our problem is that our HW can only perform 32b rd/wr accesses > So we can't use readw/readb/writew/writeb... > >
Sorry, my mistake, I meant Cavium not Qualcomm. See https://lkml.org/lkml/2016/2/5/689 for the patches.
Arnd
| |