Messages in this thread | | | Subject | Re: [PATCH 1/6] irqchip: add the Alpine MSIX interrupt controller | From | Marc Zyngier <> | Date | Mon, 8 Feb 2016 10:32:08 +0000 |
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On 08/02/16 10:26, Antoine Tenart wrote: >>> +static int alpine_msix_init(struct device_node *node, >>> + struct device_node *parent) >>> +{ >>> + struct alpine_msix_data *priv; >>> + struct resource res; >>> + int ret; >>> + >>> + priv = kzalloc(sizeof(*priv), GFP_KERNEL); >>> + if (!priv) >>> + return -ENOMEM; >>> + >>> + spin_lock_init(&priv->msi_map_lock); >>> + >>> + ret = of_address_to_resource(node, 0, &res); >>> + if (ret) { >>> + pr_err("Failed to allocate resource\n"); >>> + goto err_priv; >>> + } >>> + >>> + priv->addr_high = upper_32_bits((u64)res.start); >>> + priv->addr_low = lower_32_bits(res.start) + ALPINE_MSIX_SPI_TARGET_CLUSTER0; >> >> This is a bit odd. If you always set bit 16, why isn't that reflected in >> the base address coming from the DT? > > The 20 least significant bits of addr_low provide direct information > regarding the interrupt destination, so I thought it would be clearer > to have this explicitly in the driver so that we know what those bits > mean.
So what is this information? TARGET_CLUSTER0 is not very expressive, and doesn't show what the alternatives are. Could you please elaborate a bit on that front?
Thanks,
M. -- Jazz is not dead. It just smells funny...
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