Messages in this thread | | | Date | Mon, 22 Feb 2016 13:45:14 +0100 | From | Jan Glauber <> | Subject | Re: [PATCH v4 4/5] arm64/perf: Enable PMCR long cycle counter bit |
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On Thu, Feb 18, 2016 at 05:34:28PM +0000, Will Deacon wrote: > On Thu, Feb 18, 2016 at 05:50:13PM +0100, Jan Glauber wrote: > > With the long cycle counter bit (LC) disabled the cycle counter is not > > working on ThunderX SOC (ThunderX only implements Aarch64). > > Also, according to documentation LC == 0 is deprecated. > > > > To keep the code simple the patch does not introduce 64 bit wide counter > > functions. Instead writing the cycle counter always sets the upper > > 32 bits so overflow interrupts are generated as before. > > > > Original patch from Andrew Pinksi <Andrew.Pinksi@caviumnetworks.com> > > What does this mean? Do we need Andrew's S-o-B, or is this a fresh patch?
Hi Will,
Please let me know if I should repost or not, FWIW I got Andrew's S-o-B on the patch.
Thanks, Jan
> Will
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