lkml.org 
[lkml]   [2016]   [Feb]   [16]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
Patch in this message
/
Date
From
SubjectRe: [PATCH v3 4/5] arm64/perf: Enable PMCR long cycle counter bit
On Mon, Feb 15, 2016 at 07:55:29PM +0000, Will Deacon wrote:
> On Wed, Feb 03, 2016 at 06:11:59PM +0100, Jan Glauber wrote:
> > @@ -768,8 +776,11 @@ static void armv8pmu_reset(void *info)
> > armv8pmu_disable_intens(idx);
> > }
> >
> > - /* Initialize & Reset PMNC: C and P bits. */
> > - armv8pmu_pmcr_write(ARMV8_PMCR_P | ARMV8_PMCR_C);
> > + /*
> > + * Initialize & Reset PMNC. Request overflow on 64 bit but
> > + * cheat in armv8pmu_write_counter().
>
> Can you expand the comment to mention that the 64-bit overflow is only
> for the cycle counter, please?

OK, how about:

/*
* Initialize & Reset PMNC. Request overflow interrupt for
* 64 bit cycle counter but cheat in armv8pmu_write_counter().
*/

Jan

> Will
\
 
 \ /
  Last update: 2016-02-16 10:01    [W:0.062 / U:0.792 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site