Messages in this thread Patch in this message | | | From | Andi Kleen <> | Subject | [PATCH] perf/x86: Fix exclusion of BTS and LBR for Goldmont | Date | Thu, 8 Dec 2016 16:14:17 -0800 |
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From: Andi Kleen <ak@linux.intel.com>
An earlier patch allowed enabling PT and LBR at the same time on Goldmont. However it also allowed enabling BTS and LBR at the same time, which is still not supported. Fix this by bypassing the check only for PT.
Marking for stable because this allows crashing kernels. Also should be merged for 4.9.
Fixes: ccbebba4c6bf ("erf/x86/intel/pt: Bypass PT vs. LBR exclusivity if the core supports it") Cc: alexander.shishkin@intel.com Cc: kan.liang@intel.com Cc: <stable@vger.kernel.org> v2: Paint bike shed differently. Signed-off-by: Andi Kleen <ak@linux.intel.com> --- arch/x86/events/core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index d0efb5cb1b00..baa1eed55e88 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -364,7 +364,7 @@ int x86_add_exclusive(unsigned int what) { int i; - if (x86_pmu.lbr_pt_coexist) + if (what == x86_lbr_exclusive_pt && x86_pmu.lbr_pt_coexist) return 0; if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) { @@ -387,7 +387,7 @@ fail_unlock: void x86_del_exclusive(unsigned int what) { - if (x86_pmu.lbr_pt_coexist) + if (what == x86_lbr_exclusive_pt && x86_pmu.lbr_pt_coexist) return; atomic_dec(&x86_pmu.lbr_exclusive[what]); -- 2.9.3
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