Messages in this thread | | | Subject | Re: [PATCH v8 3/3] fpga: Add support for Lattice iCE40 FPGAs | From | Marek Vasut <> | Date | Wed, 9 Nov 2016 19:39:59 +0100 |
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On 11/09/2016 07:37 PM, Joel Holdsworth wrote: > On 09/11/16 05:01, Marek Vasut wrote: >> On 11/08/2016 06:30 PM, Joel Holdsworth wrote: >>>>>> On the whole, I don't think the zero-length transfers are too >>>>>> egregiously bad, and all the alternatives seem worse to me. >>>>> >>>>> So why not turn the CS line into GPIO and just toggle the GPIO? >>>> >>>> Does that work with *all* SPI controllers? >>>> >>> >>> It does not - no. See my other email. >> >> And is that line an actual CS of that lattice chip or a generic input >> which almost works like CS? >> > > I mean a generic output vs. a special CS output built into the SPI > master of the application processor. Take a look at how spi_set_cs(..) > works:
No. I am asking whether the signal which is INPUT on the iCE40 side is really a chipselect signal for the SPI bus OR something which mostly behaves/looks like a chipselect but is not really a chipselect.
> https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/drivers/spi/spi.c?id=refs/tags/v4.9-rc4#n695 > > > static void spi_set_cs(struct spi_device *spi, bool enable) > { > if (spi->mode & SPI_CS_HIGH) > enable = !enable; > > if (gpio_is_valid(spi->cs_gpio)) > gpio_set_value(spi->cs_gpio, !enable); > else if (spi->master->set_cs) > spi->master->set_cs(spi, !enable); > } > > So on some SPI masters, spi->master->set_cs is handled separately from > normal GPIOs. Hence why I want to use this machinery, rather than doing > it with a GPIO.
This is not relevant. FYI: using separate GPIO as a SPI chip select has it's own problems.
-- Best regards, Marek Vasut
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