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SubjectRe: [PATCH v8: 1/4] x86/msr: Add MSR_MISC_FEATURE_ENABLES and PHIR3MWAIT bit
On Tue, Nov 01, 2016 at 11:14:47AM +0100, Grzegorz Andrejczuk wrote:
> Intel Xeon Phi x200 (codenamed Knights Landing) allows to enable
> MONITOR and MWAIT instructions outside of ring 0.
>
> The feature is controlled by MSR MISC_FEATURE_ENABLES (0x140).
> Setting bit 1 of this register enables it, so MONITOR and MWAIT
> instructions do not cause invalid-opcode exceptions when invoked
> outside of ring 0.
> The feature MSR is not yet documented in the SDM. Here is
> the relevant documentation:
>
> Hex Dec Name Scope
> 140H 320 MISC_FEATURE_ENABLES Thread
> 0 Reserved
> 1 if set to 1, the MONITOR and MWAIT instructions do not
> cause invalid-opcode exceptions when executed with CPL > 0
> or in virtual-8086 mode. If MWAIT is executed when CPL > 0
> or in virtual-8086 mode, and if EAX indicates a C-state
> other than C0 or C1, the instruction operates as if EAX
> indicated the C-state C1.
> 63:2 Reserved
>
> Signed-off-by: Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com>
> ---
> arch/x86/include/asm/msr-index.h | 5 +++++
> 1 file changed, 5 insertions(+)

Reviewed-by: Borislav Petkov <bp@suse.de>

--
Regards/Gruss,
Boris.

SUSE Linux GmbH, GF: Felix Imendörffer, Jane Smithard, Graham Norton, HRB 21284 (AG Nürnberg)
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