Messages in this thread | | | Subject | Re: [PATCH V3 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table | From | Jon Hunter <> | Date | Thu, 3 Nov 2016 13:45:39 +0000 |
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On 27/10/16 15:01, Mirza Krak wrote: > From: Mirza Krak <mirza.krak@gmail.com> > > Add TEGRA20_CLK_NOR to init table and set default rate to 92 MHz which > is max rate. > > The maximum rate value of 92 MHz is pulled from the downstream L4T > kernel. > > Signed-off-by: Mirza Krak <mirza.krak@gmail.com> > Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> > Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Cheers Jon
-- nvpublic
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