Messages in this thread | | | From | Stephane Eranian <> | Date | Tue, 29 Nov 2016 10:11:23 -0800 | Subject | Re: [PATCH] perf/x86: fix event counter update issue |
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On Tue, Nov 29, 2016 at 9:30 AM, Peter Zijlstra <peterz@infradead.org> wrote: > On Tue, Nov 29, 2016 at 09:20:10AM -0800, Stephane Eranian wrote: >> Max period is limited by the number of bits the kernel can write to an MSR. >> Used to be 31, now it is 47 for core PMU as per patch pointed to by Kan. > > No, I think it sets it to 48 now, which is the problem. It should be 1 > bit less than the total width. > > So something like so. > > diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c > index a74a2dbc0180..cb8522290e6a 100644 > --- a/arch/x86/events/intel/core.c > +++ b/arch/x86/events/intel/core.c > @@ -4034,7 +4034,7 @@ __init int intel_pmu_init(void) > > /* Support full width counters using alternative MSR range */ > if (x86_pmu.intel_cap.full_width_write) { > - x86_pmu.max_period = x86_pmu.cntval_mask; > + x86_pmu.max_period = x86_pmu.cntval_mask >> 1; > x86_pmu.perfctr = MSR_IA32_PMC0; > pr_cont("full-width counters, "); > } Ah, yes! That would make it consistent with the other Intel PMU settings I see in intel/core.c such as for intel_core_pmu.max_period = (1<<31) -1 which is 0x7ffffff whereas now I see max_period of 0x0000ffffffffffff instead of 0x7fffffffffff. So I think Peter's patch is required no matter what.
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