Messages in this thread | | | Date | Fri, 18 Nov 2016 10:16:26 +0000 | From | Will Deacon <> | Subject | Re: [RFC][PATCH 7/7] kref: Implement using refcount_t |
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On Fri, Nov 18, 2016 at 04:26:34PM +0800, Boqun Feng wrote: > On Thu, Nov 17, 2016 at 04:36:24PM +0000, Will Deacon wrote: > > On Thu, Nov 17, 2016 at 05:11:10PM +0100, Peter Zijlstra wrote: > > > On Thu, Nov 17, 2016 at 12:08:36PM +0000, Will Deacon wrote: > > > > All sounds reasonable to me. It's worth pointing out that you can't create > > > > order using a control dependency hanging off the status flag of a > > > > store-conditional, but the code in question here has the dependency from > > > > the loaded value, which is sufficient. > > > > > > Yeah, I'm always surprised by that 'feature'. Is that ARM specific? Or > > > so more LL/SC archs have this? > > > > In general, I'm not sure, but I think PPC does allow for the control > > dependency. > > > > You guys mean the "control dependency" from a sc to subsequent WRITE, > like in the following litmus? > > PPC sc-control > "" > { > 0:r11=x;0:r12=y;0:r3=1;0:r10=0; > 1:r11=x;1:r12=y; > } > > P0 | P1 ; > lwarx r2, r10, r11 | lwz r2, 0(r12) ; > stwcx. r3, r10, r11 | lwsync ; > bne Fail | ; > stw r3, 0(r12) | lwz r1, 0(r11) ; > Fail: | ; > > exists > (1:r2 = 1 /\ x = 1 /\ 1:r1 = 0) > > PPCMEM and herd both said the exists-clause could be triggered > "Sometimes". > > And ISA said: > > """ > Because a Store Conditional instruction may complete before its store > has been performed, a conditional Branch instruction that depends on the > CR0 value set by a Store Conditional instruction does not order the > Store Conditional's store with respect to storage accesses caused by > instructions that follow the Branch. > """ > > So ppc doesn't honor this "control dependency". ;-)
Oh, wow! I was feeling like the odd duck after talking to paulmck and Alan Stern about this at LPC, but now it looks like I have company on the island of misfit memory models.
Will
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