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    SubjectRe: [PATCH v3 05/18] Documentation, x86: Documentation for Intel resource allocation user interface
    On Sat, Oct 08, 2016 at 12:12:07PM -0500, Nilay Vaish wrote:
    > On 7 October 2016 at 21:45, Fenghua Yu <fenghua.yu@intel.com> wrote:
    > > From: Fenghua Yu <fenghua.yu@intel.com>
    > >
    > > +L3 details (code and data prioritization disabled)
    > > +--------------------------------------------------
    > > +With CDP disabled the L3 schemata format is:
    > > +
    > > + L3:<cache_id0>=<cbm>;<cache_id1>=<cbm>;...
    > > +
    > > +L3 details (CDP enabled via mount option to resctrl)
    > > +----------------------------------------------------
    > > +When CDP is enabled, you need to specify separate cache bit masks for
    > > +code and data access. The generic format is:
    > > +
    > > + L3:<cache_id0>=<d_cbm>,<i_cbm>;<cache_id1>=<d_cbm>,<i_cbm>;...
    >
    > Can we drop L3 here and instead say:
    > L<level>:<cache_id0>=<d_cbm>,<i_cbm>;<cache_id1>=<d_cbm>,<i_cbm>;...
    >
    > and similarly for without CDP as well.

    L3 and L2 are similar but different. L2 doesn't have CDP feature. It would
    be better to talk them separately here.

    Thanks.

    -Fenghua

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