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    Subject[PATCH v3 03/18] x86, intel_cacheinfo: Enable cache id in x86
    Date
    From: Fenghua Yu <fenghua.yu@intel.com>

    Cache id is retrieved from APIC ID and CPUID leaf 4 on x86.

    For more details see the section on "Cache ID Extraction Parameters" in
    "Intel 64 Architecture Processor Topology Enumeration" at
    https://software.intel.com/sites/default/files/63/1a/Kuo_CpuTopology_rc1.rh1.final.pdf

    Also "Intel 64 and IA-32 Architectures Software Developer's Manual" volume 2,
    table 3-18 "information Returned by CPUID Instruction" at
    http://www.intel.com/sdm

    Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
    Signed-off-by: Tony Luck <tony.luck@intel.com>
    ---
    arch/x86/kernel/cpu/intel_cacheinfo.c | 20 ++++++++++++++++++++
    1 file changed, 20 insertions(+)

    diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
    index de6626c..8dc5720 100644
    --- a/arch/x86/kernel/cpu/intel_cacheinfo.c
    +++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
    @@ -153,6 +153,7 @@ struct _cpuid4_info_regs {
    union _cpuid4_leaf_eax eax;
    union _cpuid4_leaf_ebx ebx;
    union _cpuid4_leaf_ecx ecx;
    + unsigned int id;
    unsigned long size;
    struct amd_northbridge *nb;
    };
    @@ -894,6 +895,8 @@ static void __cache_cpumap_setup(unsigned int cpu, int index,
    static void ci_leaf_init(struct cacheinfo *this_leaf,
    struct _cpuid4_info_regs *base)
    {
    + this_leaf->id = base->id;
    + this_leaf->attributes = CACHE_ID;
    this_leaf->level = base->eax.split.level;
    this_leaf->type = cache_type_map[base->eax.split.type];
    this_leaf->coherency_line_size =
    @@ -920,6 +923,22 @@ static int __init_cache_level(unsigned int cpu)
    return 0;
    }

    +/*
    + * The max shared threads number comes from CPUID.4:EAX[25-14] with input
    + * ECX as cache index. Then right shift apicid by the number's order to get
    + * cache id for this cache node.
    + */
    +static void get_cache_id(int cpu, struct _cpuid4_info_regs *id4_regs)
    +{
    + struct cpuinfo_x86 *c = &cpu_data(cpu);
    + unsigned long num_threads_sharing;
    + int index_msb;
    +
    + num_threads_sharing = 1 + id4_regs->eax.split.num_threads_sharing;
    + index_msb = get_count_order(num_threads_sharing);
    + id4_regs->id = c->apicid >> index_msb;
    +}
    +
    static int __populate_cache_leaves(unsigned int cpu)
    {
    unsigned int idx, ret;
    @@ -931,6 +950,7 @@ static int __populate_cache_leaves(unsigned int cpu)
    ret = cpuid4_cache_lookup_regs(idx, &id4_regs);
    if (ret)
    return ret;
    + get_cache_id(cpu, &id4_regs);
    ci_leaf_init(this_leaf++, &id4_regs);
    __cache_cpumap_setup(cpu, idx, &id4_regs);
    }
    --
    2.5.0
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