Messages in this thread Patch in this message | | | From | Yangbo Lu <> | Subject | [v13, 1/8] dt: bindings: update Freescale DCFG compatible | Date | Fri, 28 Oct 2016 11:32:27 +0800 |
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Update Freescale DCFG compatible with 'fsl,<chip>-dcfg' instead of 'fsl,ls1021a-dcfg' to include more chips such as ls1021a, ls1043a, and ls2080a.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Scott Wood <oss@buserror.net> --- Changes for v8: - Added this patch Changes for v9: - Added a list for the possible compatibles Changes for v10: - None Changes for v11: - Added 'Acked-by: Rob Herring' - Updated commit message by Scott Changes for v12: - None Changes for v13: - None --- Documentation/devicetree/bindings/arm/fsl.txt | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt index dbbc095..713c1ae 100644 --- a/Documentation/devicetree/bindings/arm/fsl.txt +++ b/Documentation/devicetree/bindings/arm/fsl.txt @@ -119,7 +119,11 @@ Freescale DCFG configuration and status for the device. Such as setting the secondary core start address and release the secondary core from holdoff and startup. Required properties: - - compatible: should be "fsl,ls1021a-dcfg" + - compatible: should be "fsl,<chip>-dcfg" + Possible compatibles: + "fsl,ls1021a-dcfg" + "fsl,ls1043a-dcfg" + "fsl,ls2080a-dcfg" - reg : should contain base address and length of DCFG memory-mapped registers Example: -- 2.1.0.27.g96db324
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