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    Subject[PATCH] x86/cpufeature: Add AVX512_4VNNIW and AVX512_4FMAPS features.
    Date
    AVX512_4VNNIW  - Vector instructions for deep learning enhanced word
    variable precision.
    AVX512_4FMAPS - Vector instructions for deep learning floating-point
    single precision.

    The new instructions are to be used in future Intel Xeon & Xeon Phi
    processors.

    The spec can be found in Intel Software Developer Manual or in
    Instruction Set Extensions Programming Reference. See
    https://software.intel.com/sites/default/files/managed/69/78/319433-025.pdf.

    Signed-off-by: Piotr Luc <piotr.luc@intel.com>
    Reviewed-by: Dave Hansen <dave.hansen@intel.com>
    Cc: Thomas Gleixner <tglx@linutronix.de>
    Cc: Ingo Molnar <mingo@redhat.com>
    Cc: "H. Peter Anvin" <hpa@zytor.com>
    Cc: x86@kernel.org
    Cc: linux-kernel@vger.kernel.org
    ---
    arch/x86/include/asm/cpufeature.h | 7 +++++--
    arch/x86/include/asm/cpufeatures.h | 6 +++++-
    arch/x86/include/asm/disabled-features.h | 3 ++-
    arch/x86/include/asm/required-features.h | 3 ++-
    arch/x86/kernel/cpu/common.c | 1 +
    arch/x86/kernel/fpu/xstate.c | 2 ++
    tools/arch/x86/include/asm/cpufeatures.h | 6 +++++-
    tools/arch/x86/include/asm/disabled-features.h | 3 ++-
    tools/arch/x86/include/asm/required-features.h | 3 ++-
    9 files changed, 26 insertions(+), 8 deletions(-)

    diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
    index 1d2b69f..617452e 100644
    --- a/arch/x86/include/asm/cpufeature.h
    +++ b/arch/x86/include/asm/cpufeature.h
    @@ -28,6 +28,7 @@ enum cpuid_leafs
    CPUID_8000_000A_EDX,
    CPUID_7_ECX,
    CPUID_8000_0007_EBX,
    + CPUID_7_EDX,
    };

    #ifdef CONFIG_X86_FEATURE_NAMES
    @@ -78,8 +79,9 @@ extern const char * const x86_bug_flags[NBUGINTS*32];
    CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 15, feature_bit) || \
    CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 16, feature_bit) || \
    CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 17, feature_bit) || \
    + CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 18, feature_bit) || \
    REQUIRED_MASK_CHECK || \
    - BUILD_BUG_ON_ZERO(NCAPINTS != 18))
    + BUILD_BUG_ON_ZERO(NCAPINTS != 19))

    #define DISABLED_MASK_BIT_SET(feature_bit) \
    ( CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 0, feature_bit) || \
    @@ -100,8 +102,9 @@ extern const char * const x86_bug_flags[NBUGINTS*32];
    CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 15, feature_bit) || \
    CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 16, feature_bit) || \
    CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 17, feature_bit) || \
    + CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 18, feature_bit) || \
    DISABLED_MASK_CHECK || \
    - BUILD_BUG_ON_ZERO(NCAPINTS != 18))
    + BUILD_BUG_ON_ZERO(NCAPINTS != 19))

    #define cpu_has(c, bit) \
    (__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \
    diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
    index 92a8308..309fd2d 100644
    --- a/arch/x86/include/asm/cpufeatures.h
    +++ b/arch/x86/include/asm/cpufeatures.h
    @@ -12,7 +12,7 @@
    /*
    * Defines x86 CPU feature bits
    */
    -#define NCAPINTS 18 /* N 32-bit words worth of info */
    +#define NCAPINTS 19 /* N 32-bit words worth of info */
    #define NBUGINTS 1 /* N 32-bit bug flags */

    /*
    @@ -286,6 +286,10 @@
    #define X86_FEATURE_SUCCOR (17*32+1) /* Uncorrectable error containment and recovery */
    #define X86_FEATURE_SMCA (17*32+3) /* Scalable MCA */

    +/* Intel-defined CPU features, CPUID level 0x00000007:0 (edx), word 18 */
    +#define X86_FEATURE_AVX512_4VNNIW (18*32+2) /* AVX-512 Neural Network Instructions */
    +#define X86_FEATURE_AVX512_4FMAPS (18*32+3) /* AVX-512 Multiply Accumulation Single precision */
    +
    /*
    * BUG word(s)
    */
    diff --git a/arch/x86/include/asm/disabled-features.h b/arch/x86/include/asm/disabled-features.h
    index 85599ad..8b45e08 100644
    --- a/arch/x86/include/asm/disabled-features.h
    +++ b/arch/x86/include/asm/disabled-features.h
    @@ -57,6 +57,7 @@
    #define DISABLED_MASK15 0
    #define DISABLED_MASK16 (DISABLE_PKU|DISABLE_OSPKE)
    #define DISABLED_MASK17 0
    -#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 18)
    +#define DISABLED_MASK18 0
    +#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 19)

    #endif /* _ASM_X86_DISABLED_FEATURES_H */
    diff --git a/arch/x86/include/asm/required-features.h b/arch/x86/include/asm/required-features.h
    index fac9a5c..6847d85 100644
    --- a/arch/x86/include/asm/required-features.h
    +++ b/arch/x86/include/asm/required-features.h
    @@ -100,6 +100,7 @@
    #define REQUIRED_MASK15 0
    #define REQUIRED_MASK16 0
    #define REQUIRED_MASK17 0
    -#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 18)
    +#define REQUIRED_MASK18 0
    +#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 19)

    #endif /* _ASM_X86_REQUIRED_FEATURES_H */
    diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
    index bcc9ccc..6e6189f 100644
    --- a/arch/x86/kernel/cpu/common.c
    +++ b/arch/x86/kernel/cpu/common.c
    @@ -675,6 +675,7 @@ void get_cpu_cap(struct cpuinfo_x86 *c)

    c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006);
    c->x86_capability[CPUID_7_ECX] = ecx;
    + c->x86_capability[CPUID_7_EDX] = edx;
    }

    /* Extended state features: level 0x0000000d */
    diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c
    index 01567aa..7dbd480 100644
    --- a/arch/x86/kernel/fpu/xstate.c
    +++ b/arch/x86/kernel/fpu/xstate.c
    @@ -73,6 +73,8 @@ void fpu__xstate_clear_all_cpu_caps(void)
    setup_clear_cpu_cap(X86_FEATURE_MPX);
    setup_clear_cpu_cap(X86_FEATURE_XGETBV1);
    setup_clear_cpu_cap(X86_FEATURE_PKU);
    + setup_clear_cpu_cap(X86_FEATURE_AVX512_4VNNIW);
    + setup_clear_cpu_cap(X86_FEATURE_AVX512_4FMAPS);
    }

    /*
    diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h
    index 92a8308..309fd2d 100644
    --- a/tools/arch/x86/include/asm/cpufeatures.h
    +++ b/tools/arch/x86/include/asm/cpufeatures.h
    @@ -12,7 +12,7 @@
    /*
    * Defines x86 CPU feature bits
    */
    -#define NCAPINTS 18 /* N 32-bit words worth of info */
    +#define NCAPINTS 19 /* N 32-bit words worth of info */
    #define NBUGINTS 1 /* N 32-bit bug flags */

    /*
    @@ -286,6 +286,10 @@
    #define X86_FEATURE_SUCCOR (17*32+1) /* Uncorrectable error containment and recovery */
    #define X86_FEATURE_SMCA (17*32+3) /* Scalable MCA */

    +/* Intel-defined CPU features, CPUID level 0x00000007:0 (edx), word 18 */
    +#define X86_FEATURE_AVX512_4VNNIW (18*32+2) /* AVX-512 Neural Network Instructions */
    +#define X86_FEATURE_AVX512_4FMAPS (18*32+3) /* AVX-512 Multiply Accumulation Single precision */
    +
    /*
    * BUG word(s)
    */
    diff --git a/tools/arch/x86/include/asm/disabled-features.h b/tools/arch/x86/include/asm/disabled-features.h
    index 85599ad..8b45e08 100644
    --- a/tools/arch/x86/include/asm/disabled-features.h
    +++ b/tools/arch/x86/include/asm/disabled-features.h
    @@ -57,6 +57,7 @@
    #define DISABLED_MASK15 0
    #define DISABLED_MASK16 (DISABLE_PKU|DISABLE_OSPKE)
    #define DISABLED_MASK17 0
    -#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 18)
    +#define DISABLED_MASK18 0
    +#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 19)

    #endif /* _ASM_X86_DISABLED_FEATURES_H */
    diff --git a/tools/arch/x86/include/asm/required-features.h b/tools/arch/x86/include/asm/required-features.h
    index fac9a5c..6847d85 100644
    --- a/tools/arch/x86/include/asm/required-features.h
    +++ b/tools/arch/x86/include/asm/required-features.h
    @@ -100,6 +100,7 @@
    #define REQUIRED_MASK15 0
    #define REQUIRED_MASK16 0
    #define REQUIRED_MASK17 0
    -#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 18)
    +#define REQUIRED_MASK18 0
    +#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 19)

    #endif /* _ASM_X86_REQUIRED_FEATURES_H */
    --
    2.10.1
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