Messages in this thread | | | From | Chen-Yu Tsai <> | Date | Thu, 28 Jan 2016 10:41:33 +0800 | Subject | Re: [PATCH RFC 11/11] clk: sunxi: rewrite sun8i-a23-mbus-clk using the simpler composite clk |
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Hi,
On Thu, Jan 28, 2016 at 1:49 AM, Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > On Mon, Jan 25, 2016 at 09:15:47PM +0800, Chen-Yu Tsai wrote: >> sun8i-a23-mbus-clk used sunxi's factors clk, which is nice for very >> complicated clocks, but is not really needed here. >> >> Convert sun8i-a23-mbus-clk to use clk_composite, as it is a gate + mux >> + divider. This makes the code easier to understand. >> >> Signed-off-by: Chen-Yu Tsai <wens@csie.org> > > Applied, thanks! > Maxime
Given your suggestion for extending and generalizing factors clk clock rate calculations, maybe we just leave this one out and use the new stuff later?
Thanks ChenYu
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