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    Subject[PATCH 4.2 020/134] MIPS: math-emu: Emulate missing BC1{EQ,NE}Z instructions
    Date
    4.2-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Markos Chandras <markos.chandras@imgtec.com>

    commit c909ca718e8f50cf484ef06a8dd935e738e8e53d upstream.

    Commit c8a34581ec09 ("MIPS: Emulate the BC1{EQ,NE}Z FPU instructions")
    added support for emulating the new R6 BC1{EQ,NE}Z branches but it missed
    the case where the instruction that caused the exception was not on a DS.

    Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
    Fixes: c8a34581ec09 ("MIPS: Emulate the BC1{EQ,NE}Z FPU instructions")
    Cc: linux-mips@linux-mips.org
    Patchwork: https://patchwork.linux-mips.org/patch/10738/
    Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

    ---
    arch/mips/math-emu/cp1emu.c | 20 +++++++++++++++++++-
    1 file changed, 19 insertions(+), 1 deletion(-)

    --- a/arch/mips/math-emu/cp1emu.c
    +++ b/arch/mips/math-emu/cp1emu.c
    @@ -1181,6 +1181,24 @@ emul:
    }
    break;

    + case bc1eqz_op:
    + case bc1nez_op:
    + if (!cpu_has_mips_r6 || delay_slot(xcp))
    + return SIGILL;
    +
    + cond = likely = 0;
    + switch (MIPSInst_RS(ir)) {
    + case bc1eqz_op:
    + if (get_fpr32(&current->thread.fpu.fpr[MIPSInst_RT(ir)], 0) & 0x1)
    + cond = 1;
    + break;
    + case bc1nez_op:
    + if (!(get_fpr32(&current->thread.fpu.fpr[MIPSInst_RT(ir)], 0) & 0x1))
    + cond = 1;
    + break;
    + }
    + goto branch_common;
    +
    case bc_op:
    if (delay_slot(xcp))
    return SIGILL;
    @@ -1207,7 +1225,7 @@ emul:
    case bct_op:
    break;
    }
    -
    +branch_common:
    set_delay_slot(xcp);
    if (cond) {
    /*



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