Messages in this thread | | | Date | Thu, 30 Jul 2015 12:40:46 +0200 | From | Peter Zijlstra <> | Subject | Re: [PATCH 1/3] perf/x86/intel/pt: Add new timing packet enables |
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On Fri, Jul 17, 2015 at 04:34:08PM +0300, Alexander Shishkin wrote: > +#define PT_CONFIG_MASK (RTIT_CTL_TSC_EN | \ > + RTIT_CTL_DISRETC | \ > + RTIT_CTL_CYCLEACC | \ > + RTIT_CTL_MTC_EN | \ > + RTIT_CTL_MTC_RANGE | \ > + RTIT_CTL_CYC_THRESH | \ > + RTIT_CTL_PSB_FREQ) >
#define RTIT_CTL_CYC (RTIT_CTL_CYCLEACC | \ RTIT_CTL_CYC_THRESH | \ RTIT_CTL_PSB_FREQ)
#define RTIT_CTL_MTC (RTIT_CTL_MTC_EN | \ RTIT_CTL_MTC_RANGE)
#define PT_CONFIG_MASK (RTIT_CTL_TSC_EN | \ RTIT_CTL_DISRETC | \ RTIT_CTL_CYC | \ RTIT_CTL_MTC)
> static bool pt_event_valid(struct perf_event *event) > { > u64 config = event->attr.config; > + u64 allowed, requested; > > if ((config & PT_CONFIG_MASK) != config) > return false; > > + if (config & > + (RTIT_CTL_CYCLEACC | RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ)) {
if (config & RTIT_CTL_CYC) {
> + if (!pt_cap_get(PT_CAP_psb_cyc)) > + return false; > + > + allowed = pt_cap_get(PT_CAP_psb_periods); > + requested = (config & RTIT_CTL_PSB_FREQ) >> > + RTIT_CTL_PSB_FREQ_OFFSET; > + if (requested && (!(allowed & BIT(requested)))) > + return false; > + > + allowed = pt_cap_get(PT_CAP_cycle_thresholds); > + requested = (config & RTIT_CTL_CYC_THRESH) >> > + RTIT_CTL_CYC_THRESH_OFFSET; > + if (requested && (!(allowed & BIT(requested)))) > + return false; > + } > + > + if (config & (RTIT_CTL_MTC_EN | RTIT_CTL_MTC_RANGE)) {
if (config & RTIT_CTL_MTC) {
> + allowed = pt_cap_get(PT_CAP_mtc_periods); > + > + if (!allowed) > + return false; > + > + requested = (config & RTIT_CTL_MTC_RANGE) >> > + RTIT_CTL_MTC_RANGE_OFFSET; > + > + if (!(allowed & BIT(requested))) > + return false; > + } > + > return true; > }
Would that make sense?
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