Messages in this thread | | | Date | Wed, 29 Jul 2015 10:23:30 +0200 | From | Michal Hocko <> | Subject | Re: Re: [V2 PATCH 1/3] x86/panic: Fix re-entrance problem due to panic on NMI |
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On Wed 29-07-15 05:48:47, 河合英宏 / KAWAI,HIDEHIRO wrote: > Hi, > > > From: linux-kernel-owner@vger.kernel.org [mailto:linux-kernel-owner@vger.kernel.org] On Behalf Of Hidehiro Kawai > > (2015/07/27 23:34), Michal Hocko wrote: > > > On Mon 27-07-15 10:58:50, Hidehiro Kawai wrote: > [...] > > > The check could be also relaxed a bit and nmi_panic would > > > return only if the ongoing panic is the current cpu when we really have > > > to return and allow the preempted panic to finish. > > > > It's reasonable. I'll do that in the next version. > > I noticed atomic_read() is insufficient. Please consider the following > scenario. > > CPU 1: call panic() in the normal context > CPU 0: call nmi_panic(), check the value of panic_cpu, then call panic() > CPU 1: set 1 to panic_cpu > CPU 0: fail to set 0 to panic_cpu, then do an infinite loop > CPU 1: call crash_kexec(), then call kdump_nmi_shootdown_cpus() > > At this point, since CPU 0 loops in NMI context, it never executes > the NMI handler registered by kdump_nmi_shootdown_cpus(). This means > that no register states are saved and no cleanups for VMX/SVM are > performed.
Yes this is true but it is no different from the current state, isn't it? So if you want to handle that then it deserves a separate patch. It is certainly not harmful wrt. panic behavior.
> So, we should still use atomic_cmpxchg() in nmi_panic() to > prevent other cpus from running panic routines.
Not sure what you mean by that.
-- Michal Hocko SUSE Labs
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