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    SubjectRe: [PATCH] x86/mm/pat: Initialize __cachemode2pte_tbl[] and __pte2cachemode_tbl[] in a bit more readable fashion
    On 03/05/2015 09:21 AM, Ingo Molnar wrote:
    >
    > ( So this patch is not directly related to gbpages, but while reading
    > arch/x86/mm/init.c I could not resist ... )
    >
    > =======================>
    >
    > The initialization of these two arrays is a bit difficult to follow:
    > restructure it optically so that a 2D structure shows which bit in
    > the PTE is set and which not.
    >
    > Also improve on comments a bit.
    >
    > No code or data changed:
    >
    > # arch/x86/mm/init.o:
    >
    > text data bss dec hex filename
    > 4585 424 29776 34785 87e1 init.o.before
    > 4585 424 29776 34785 87e1 init.o.after
    >
    > md5:
    > a82e11ff58bcfd0af3a94662a701f65d init.o.before.asm
    > a82e11ff58bcfd0af3a94662a701f65d init.o.after.asm
    >
    > Cc: Andy Lutomirski <luto@amacapital.net>
    > Cc: Dave Hansen <dave.hansen@linux.intel.com>
    > Cc: Jan Beulich <JBeulich@suse.com>
    > Cc: Juergen Gross <jgross@suse.com>
    > Cc: Linus Torvalds <torvalds@linux-foundation.org>
    > Cc: Luis R. Rodriguez <mcgrof@suse.com>
    > Cc: Toshi Kani <toshi.kani@hp.com>
    > Cc: linux-kernel@vger.kernel.org
    > Signed-off-by: Ingo Molnar <mingo@kernel.org>

    Reviewed-by: Juergen Gross <jgross@suse.com>

    > ---
    > arch/x86/mm/init.c | 40 ++++++++++++++++++++++------------------
    > 1 file changed, 22 insertions(+), 18 deletions(-)
    >
    > diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c
    > index 6dc85d51cd98..4469563f8c3b 100644
    > --- a/arch/x86/mm/init.c
    > +++ b/arch/x86/mm/init.c
    > @@ -29,29 +29,33 @@
    >
    > /*
    > * Tables translating between page_cache_type_t and pte encoding.
    > - * Minimal supported modes are defined statically, modified if more supported
    > - * cache modes are available.
    > - * Index into __cachemode2pte_tbl is the cachemode.
    > - * Index into __pte2cachemode_tbl are the caching attribute bits of the pte
    > - * (_PAGE_PWT, _PAGE_PCD, _PAGE_PAT) at index bit positions 0, 1, 2.
    > + *
    > + * Minimal supported modes are defined statically, they are modified
    > + * during bootup if more supported cache modes are available.
    > + *
    > + * Index into __cachemode2pte_tbl[] is the cachemode.
    > + *
    > + * Index into __pte2cachemode_tbl[] are the caching attribute bits of the pte
    > + * (_PAGE_PWT, _PAGE_PCD, _PAGE_PAT) at index bit positions 0, 1, 2.
    > */
    > uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM] = {
    > - [_PAGE_CACHE_MODE_WB] = 0,
    > - [_PAGE_CACHE_MODE_WC] = _PAGE_PWT,
    > - [_PAGE_CACHE_MODE_UC_MINUS] = _PAGE_PCD,
    > - [_PAGE_CACHE_MODE_UC] = _PAGE_PCD | _PAGE_PWT,
    > - [_PAGE_CACHE_MODE_WT] = _PAGE_PCD,
    > - [_PAGE_CACHE_MODE_WP] = _PAGE_PCD,
    > + [_PAGE_CACHE_MODE_WB ] = 0 | 0 ,
    > + [_PAGE_CACHE_MODE_WC ] = _PAGE_PWT | 0 ,
    > + [_PAGE_CACHE_MODE_UC_MINUS] = 0 | _PAGE_PCD,
    > + [_PAGE_CACHE_MODE_UC ] = _PAGE_PWT | _PAGE_PCD,
    > + [_PAGE_CACHE_MODE_WT ] = 0 | _PAGE_PCD,
    > + [_PAGE_CACHE_MODE_WP ] = 0 | _PAGE_PCD,
    > };
    > EXPORT_SYMBOL(__cachemode2pte_tbl);
    > +
    > uint8_t __pte2cachemode_tbl[8] = {
    > - [__pte2cm_idx(0)] = _PAGE_CACHE_MODE_WB,
    > - [__pte2cm_idx(_PAGE_PWT)] = _PAGE_CACHE_MODE_WC,
    > - [__pte2cm_idx(_PAGE_PCD)] = _PAGE_CACHE_MODE_UC_MINUS,
    > - [__pte2cm_idx(_PAGE_PWT | _PAGE_PCD)] = _PAGE_CACHE_MODE_UC,
    > - [__pte2cm_idx(_PAGE_PAT)] = _PAGE_CACHE_MODE_WB,
    > - [__pte2cm_idx(_PAGE_PWT | _PAGE_PAT)] = _PAGE_CACHE_MODE_WC,
    > - [__pte2cm_idx(_PAGE_PCD | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC_MINUS,
    > + [__pte2cm_idx( 0 | 0 | 0 )] = _PAGE_CACHE_MODE_WB,
    > + [__pte2cm_idx(_PAGE_PWT | 0 | 0 )] = _PAGE_CACHE_MODE_WC,
    > + [__pte2cm_idx( 0 | _PAGE_PCD | 0 )] = _PAGE_CACHE_MODE_UC_MINUS,
    > + [__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | 0 )] = _PAGE_CACHE_MODE_UC,
    > + [__pte2cm_idx( 0 | 0 | _PAGE_PAT)] = _PAGE_CACHE_MODE_WB,
    > + [__pte2cm_idx(_PAGE_PWT | 0 | _PAGE_PAT)] = _PAGE_CACHE_MODE_WC,
    > + [__pte2cm_idx(0 | _PAGE_PCD | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC_MINUS,
    > [__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC,
    > };
    > EXPORT_SYMBOL(__pte2cachemode_tbl);
    > --
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