Messages in this thread Patch in this message | | | From | Mikko Perttunen <> | Subject | [PATCH v8 12/18] ARM: tegra: Enable the DFLL on the Jetson TK1 | Date | Sun, 1 Mar 2015 14:44:35 +0200 |
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From: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Add the board-specific properties of the DFLL for the Jetson TK1 board. On this board, the DFLL will take control of the sd0 regulator on the on-board AS3722 PMIC.
Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi> --- v8: - Changed dfll@ -> clock@
arch/arm/boot/dts/tegra124-jetson-tk1.dts | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index dbfaba0..f0888dd 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -1509,7 +1509,7 @@ vin-ldo9-10-supply = <&vdd_5v0_sys>; vin-ldo11-supply = <&vdd_3v3_run>; - sd0 { + vdd_cpu: sd0 { regulator-name = "+VDD_CPU_AP"; regulator-min-microvolt = <700000>; regulator-max-microvolt = <1400000>; @@ -1737,6 +1737,13 @@ non-removable; }; + /* CPU DFLL clock */ + clock@0,70110000 { + status = "okay"; + vdd-cpu-supply = <&vdd_cpu>; + nvidia,i2c-fs-rate = <400000>; + }; + ahub@0,70300000 { i2s@0,70301100 { status = "okay"; -- 2.3.0
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