Messages in this thread | | | Date | Thu, 05 Feb 2015 01:14:46 +0300 | From | Sergei Shtylyov <> | Subject | Re: [PATCH] clk: shmobile: div6: Avoid division by zero in .round_rate() |
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Hello.
On 02/05/2015 01:04 AM, Sergei Shtylyov wrote:
>>>>> Anyone may call clk_round_rate() with a zero rate value, so we have to >>>>> protect against that.
>>>>> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
>>>> Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
>>>> I agree that this should not be fixed in the core because the fixup is >>>> really driver dependant.
>>> Dunno, zero frequency seems generally insane to me.
>> It is useful to find the lowest frequency a clock can support. Basically >> it is a search for the floor frequency.
> Why not just use 1? Or are you assuming that some hardware could actually > support 0 Hz?
Replying to myself: yes, this has happened to me, when I forgot to override the EXTAL frequency in the board .dts file (default was 0).
>> Regards, >> Mike
WBR, Sergei
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