Messages in this thread | | | Date | Mon, 23 Feb 2015 08:32:58 +0100 | From | Sascha Hauer <> | Subject | Re: [PATCH 1/3] clk: divider: fix calculation of maximal parent rate for a given divider |
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On Sat, Feb 21, 2015 at 11:40:23AM +0100, Uwe Kleine-König wrote: > The rate provided at the output of a clk-divider is calculated as: > > DIV_ROUND_UP(parent_rate, div) > > since commit b11d282dbea2 (clk: divider: fix rate calculation for > fractional rates). So to yield a rate not bigger than r parent_rate > must be <= r * div. > > The effect of choosing a parent rate that is too big as was done before > this patch results in wrongly ruling out good dividers. > > Note that this is not a complete fix as __clk_round_rate might return a > value >= its 2nd parameter. Also for dividers with > CLK_DIVIDER_ROUND_CLOSEST set the calculation is not accurate. But this > fixes the test case by Sascha Hauer that uses a chain of three dividers > under a fixed clock. > > Fixes: b11d282dbea2 (clk: divider: fix rate calculation for fractional rates) > Suggested-by: Sascha Hauer <s.hauer@pengutronix.de> > Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
This gives clk_round_rate/clk_set_rate on dividers a consistent behaviour. Also the testcases I posted seem to work fine.
The only thing that might not be nice is that when a divider can only output fractional rates then the next higher integer value has to be used for clk_round_rate/clk_set_rate. A consumer should probably make no assumptions whether 333.333Hz is rounded up or down and use 334Hz to be sure anyway.
Sascha
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