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    SubjectRe: [PATCHv2 2/2] usb: pci-quirks: register USB mux found on Cherrytrail SOC
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    Hello.

    On 12/03/2015 12:29 PM, Heikki Krogerus wrote:

    > Intel Braswell/Cherrytrail has an internal mux that shares
    > one USB port between USB Device Controller and xHCI. The
    > same mux is found on several SOCs from Intel, but only on
    > a few Cherrytrail based platforms the OS is expected to
    > configure it. Normally BIOS takes care of it.
    >
    > The driver for the mux is an "extcon" driver. With this we
    > only register the mux if it's detected.

    Hm, I had somewhat identical case on the Renesas SoC: the 2 channel mux
    was mapped to the USB device PHY register space, so I chose to implement a PHY
    driver, not extcon...
    I don't quite understand how mux maps to the extcon core -- doesn't it
    provide support only the input signals?

    > Suggested-by: Lu Baolu <baolu.lu@linux.intel.com>
    > Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
    > ---
    > drivers/usb/host/pci-quirks.c | 26 +++++++++++++++++++++++++-
    > 1 file changed, 25 insertions(+), 1 deletion(-)
    >
    > diff --git a/drivers/usb/host/pci-quirks.c b/drivers/usb/host/pci-quirks.c
    > index 26cb8c8..ee875e1 100644
    > --- a/drivers/usb/host/pci-quirks.c
    > +++ b/drivers/usb/host/pci-quirks.c
    [...]
    > @@ -1022,9 +1023,32 @@ static void quirk_usb_handoff_xhci(struct pci_dev *pdev)
    > writel(val, base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET);
    >
    > hc_init:
    > - if (pdev->vendor == PCI_VENDOR_ID_INTEL)
    > + if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
    > usb_enable_intel_xhci_ports(pdev);
    >
    > + /*
    > + * Initialize the internal mux that shares a port between USB
    > + * Device Controller and xHCI on platforms that have it.
    > + */
    > +#define XHCI_INTEL_VENDOR_CAPS 192
    > +#define XHCI_INTEL_USB_MUX_OFFSET 0x80d8
    > + if (xhci_find_next_ext_cap(base, 0, XHCI_INTEL_VENDOR_CAPS)) {
    > + struct intel_usb_mux *mux;
    > + struct resource r;
    > +
    > + r.start = pci_resource_start(pdev, 0) +
    > + XHCI_INTEL_USB_MUX_OFFSET;
    > + r.end = r.start + 8;
    > + r.flags = IORESOURCE_MEM;
    > +
    > + mux = intel_usb_mux_register(&pdev->dev, &r);
    > + if (IS_ERR(mux) && PTR_ERR(mux) == -ENOTSUPP)

    I think you can drop IS_ERR() check here...

    > + dev_dbg(&pdev->dev, "USB mux not supported\n");
    > + else if (IS_ERR(mux))
    > + dev_err(&pdev->dev, "failed to register mux\n");
    > + }
    > + }
    > +
    > op_reg_base = base + XHCI_HC_LENGTH(readl(base));
    >
    > /* Wait for the host controller to be ready before writing any

    MBR, Sergei



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