Messages in this thread | | | Date | Wed, 2 Dec 2015 14:28:27 -0800 | Subject | Re: [PATCH v1 2/2] perf/x86: add cycles:pp alias for Intel Atom | From | Stephane Eranian <> |
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On Wed, Dec 2, 2015 at 11:37 AM, Liang, Kan <kan.liang@intel.com> wrote: > > >> -----Original Message----- >> From: Stephane Eranian [mailto:eranian@google.com] >> Sent: Wednesday, December 02, 2015 1:28 PM >> To: linux-kernel@vger.kernel.org >> Cc: acme@redhat.com; peterz@infradead.org; mingo@elte.hu; >> ak@linux.intel.com; Liang, Kan >> Subject: [PATCH v1 2/2] perf/x86: add cycles:pp alias for Intel Atom >> >> This patch updates the PEBS support for Intel Atom to provide an alias for >> the cycles:pp event used by perf record/top by default nowadays. >> >> On Atom only INST_RETIRED:ANY supports PEBS, so we use this event >> instead with a large cmask to count cycles. >> >> Signed-off-by: Stephane Eranian <eranian@google.com> >> --- >> arch/x86/kernel/cpu/perf_event_intel.c | 30 >> ++++++++++++++++++++++++++++++ >> arch/x86/kernel/cpu/perf_event_intel_ds.c | 2 ++ >> 2 files changed, 32 insertions(+) >> >> diff --git a/arch/x86/kernel/cpu/perf_event_intel.c >> b/arch/x86/kernel/cpu/perf_event_intel.c >> index 61f2577..7ff1e30 100644 >> --- a/arch/x86/kernel/cpu/perf_event_intel.c >> +++ b/arch/x86/kernel/cpu/perf_event_intel.c >> @@ -2475,6 +2475,35 @@ static void intel_pebs_aliases_snb(struct >> perf_event *event) >> } >> } >> >> +static void intel_pebs_aliases_atom(struct perf_event *event) { >> + if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { >> + /* >> + * Use an alternative encoding for >> CPU_CLK_UNHALTED.THREAD_P >> + * (0x003c) so that we can use it with PEBS. >> + * >> + * The regular CPU_CLK_UNHALTED.THREAD_P event >> (0x003c) isn't >> + * PEBS capable. However we can use UOPS_RETIRED.ALL >> + * (0x01c2), which is a PEBS capable event, to get the same > > The comment isn't consistent with the code. > >> + * count. >> + * >> + * INST_RETIRED.ANY counts the number of cycles that >> retires >> + * CNTMASK instructions. By setting CNTMASK to a value >> (16) >> + * larger than the maximum number of instructions that >> can be >> + * retired per cycle (4) and then inverting the condition, we >> + * count all cycles that retire 16 or less instructions, which >> + * is every cycle. >> + * >> + * Thereby we gain a PEBS capable cycle counter. >> + */ >> + u64 alt_config = >> X86_CONFIG(.event=0xc0, .umask=0x00, .inv=1, >> +.cmask=16); >> + >> + alt_config |= (event->hw.config & >> ~X86_RAW_EVENT_MASK); >> + event->hw.config = alt_config; >> + } >> +} >> + >> + >> static unsigned long intel_pmu_free_running_flags(struct perf_event >> *event) { >> unsigned long flags = x86_pmu.free_running_flags; @@ -3332,6 >> +3361,7 @@ __init int intel_pmu_init(void) >> >> x86_pmu.event_constraints = >> intel_gen_event_constraints; >> x86_pmu.pebs_constraints = >> intel_atom_pebs_event_constraints; >> + x86_pmu.pebs_aliases = intel_pebs_aliases_atom; > > intel_pebs_aliases_atom looks the same as intel_pebs_aliases_core2. > Why not reuse the existing intel_pebs_aliases_core2? > Sure, will do this in V2.
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