Messages in this thread | | | Date | Sun, 8 Nov 2015 00:52:33 +0100 (CET) | From | Thomas Gleixner <> | Subject | Re: [PATCH v2 04/19] irqchip: add nps Internal and external irqchips |
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Noam,
On Sat, 7 Nov 2015, Noam Camus wrote: > >From: Thomas Gleixner <tglx@linutronix.de> > >> + write_aux_reg(AUX_IENABLE, ienb); > > >I can see how that works for per cpu interrupts, but what happens if > >two cpus run that concurrent for two different interrupts? > > Each CPU got its own HW copy of auxiliary register IENABLE, so > concurrent access won't be a trouble.
Please put a comment into the code explaining it.
Thanks,
tglx
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