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SubjectRe: [PATCH 3/3] comedi: driver: Fix - BIT macro used coding style issue
On 06/11/15 13:54, Ranjith T wrote:
> Is this patch is fine?..Because I didn't get any reply for this patch

Your patch numbering sucks. Isolated patches should just use [PATCH],
not [PATCH 3/3], [PATCH 4/4], etc.

Also, could you mention the name of the COMEDI driver in the patch
title, e.g.:

[PATCH] comedi: pcmmio: Fix coding style - use BIT macro

> Thanks,
> Ranjith.T.
>
> On Thu, Nov 5, 2015 at 9:27 PM, Ranjith <ranjithece24@gmail.com> wrote:
>> BIT macro is used for defining bit location instead of shifting
>> operator - coding style issue
>>
>> Signed-off-by: Ranjith T <ranjithece24@gmail.com>
>> ---
>> drivers/staging/comedi/drivers/pcmmio.c | 42 +++++++++++++++----------------
>> 1 file changed, 21 insertions(+), 21 deletions(-)
>>
>> diff --git a/drivers/staging/comedi/drivers/pcmmio.c b/drivers/staging/comedi/drivers/pcmmio.c
>> index 10472e6..807795c 100644
>> --- a/drivers/staging/comedi/drivers/pcmmio.c
>> +++ b/drivers/staging/comedi/drivers/pcmmio.c
>> @@ -84,25 +84,25 @@
>> #define PCMMIO_AI_LSB_REG 0x00
>> #define PCMMIO_AI_MSB_REG 0x01
>> #define PCMMIO_AI_CMD_REG 0x02
>> -#define PCMMIO_AI_CMD_SE (1 << 7)
>> -#define PCMMIO_AI_CMD_ODD_CHAN (1 << 6)
>> +#define PCMMIO_AI_CMD_SE BIT(7)

The whitespace is a bit strange here as 'BIT(7)' no longer lines up with
the surrounding lines.

>> +#define PCMMIO_AI_CMD_ODD_CHAN BIT(6)
>> #define PCMMIO_AI_CMD_CHAN_SEL(x) (((x) & 0x3) << 4)
>> #define PCMMIO_AI_CMD_RANGE(x) (((x) & 0x3) << 2)
>> #define PCMMIO_RESOURCE_REG 0x02
>> #define PCMMIO_RESOURCE_IRQ(x) (((x) & 0xf) << 0)
>> #define PCMMIO_AI_STATUS_REG 0x03
>> -#define PCMMIO_AI_STATUS_DATA_READY (1 << 7)
>> -#define PCMMIO_AI_STATUS_DATA_DMA_PEND (1 << 6)
>> -#define PCMMIO_AI_STATUS_CMD_DMA_PEND (1 << 5)
>> -#define PCMMIO_AI_STATUS_IRQ_PEND (1 << 4)
>> -#define PCMMIO_AI_STATUS_DATA_DRQ_ENA (1 << 2)
>> -#define PCMMIO_AI_STATUS_REG_SEL (1 << 3)
>> -#define PCMMIO_AI_STATUS_CMD_DRQ_ENA (1 << 1)
>> -#define PCMMIO_AI_STATUS_IRQ_ENA (1 << 0)
>> +#define PCMMIO_AI_STATUS_DATA_READY BIT(7)
>> +#define PCMMIO_AI_STATUS_DATA_DMA_PEND BIT(6)
>> +#define PCMMIO_AI_STATUS_CMD_DMA_PEND BIT(5)
>> +#define PCMMIO_AI_STATUS_IRQ_PEND BIT(4)
>> +#define PCMMIO_AI_STATUS_DATA_DRQ_ENA BIT(2)

The 'BIT(2)' also does not line up with the surrounding lines.

>> +#define PCMMIO_AI_STATUS_REG_SEL BIT(3)
>> +#define PCMMIO_AI_STATUS_CMD_DRQ_ENA BIT(1)
>> +#define PCMMIO_AI_STATUS_IRQ_ENA BIT(0)
>> #define PCMMIO_AI_RES_ENA_REG 0x03
>> -#define PCMMIO_AI_RES_ENA_CMD_REG_ACCESS (0 << 3)
>> -#define PCMMIO_AI_RES_ENA_AI_RES_ACCESS (1 << 3)
>> -#define PCMMIO_AI_RES_ENA_DIO_RES_ACCESS (1 << 4)
>> +#define PCMMIO_AI_RES_ENA_CMD_REG_ACCESS 0
>> +#define PCMMIO_AI_RES_ENA_AI_RES_ACCESS BIT(3)
>> +#define PCMMIO_AI_RES_ENA_DIO_RES_ACCESS BIT(4)
>> #define PCMMIO_AI_2ND_ADC_OFFSET 0x04
>>
>> #define PCMMIO_AO_LSB_REG 0x08
>> @@ -125,14 +125,14 @@
>> #define PCMMIO_AO_CMD_CHAN_SEL(x) (((x) & 0x03) << 1)
>> #define PCMMIO_AO_CMD_CHAN_SEL_ALL (0x0f << 0)
>> #define PCMMIO_AO_STATUS_REG 0x0b
>> -#define PCMMIO_AO_STATUS_DATA_READY (1 << 7)
>> -#define PCMMIO_AO_STATUS_DATA_DMA_PEND (1 << 6)
>> -#define PCMMIO_AO_STATUS_CMD_DMA_PEND (1 << 5)
>> -#define PCMMIO_AO_STATUS_IRQ_PEND (1 << 4)
>> -#define PCMMIO_AO_STATUS_DATA_DRQ_ENA (1 << 2)
>> -#define PCMMIO_AO_STATUS_REG_SEL (1 << 3)
>> -#define PCMMIO_AO_STATUS_CMD_DRQ_ENA (1 << 1)
>> -#define PCMMIO_AO_STATUS_IRQ_ENA (1 << 0)
>> +#define PCMMIO_AO_STATUS_DATA_READY BIT(7)
>> +#define PCMMIO_AO_STATUS_DATA_DMA_PEND BIT(6)
>> +#define PCMMIO_AO_STATUS_CMD_DMA_PEND BIT(5)
>> +#define PCMMIO_AO_STATUS_IRQ_PEND BIT(4)
>> +#define PCMMIO_AO_STATUS_DATA_DRQ_ENA BIT(2)
>> +#define PCMMIO_AO_STATUS_REG_SEL BIT(3)
>> +#define PCMMIO_AO_STATUS_CMD_DRQ_ENA BIT(1)
>> +#define PCMMIO_AO_STATUS_IRQ_ENA BIT(0)
>> #define PCMMIO_AO_RESOURCE_ENA_REG 0x0b
>> #define PCMMIO_AO_2ND_DAC_OFFSET 0x04
>>
>> --
>> 1.7.10.4
>>


--
-=( Ian Abbott @ MEV Ltd. E-mail: <abbotti@mev.co.uk> )=-
-=( Web: http://www.mev.co.uk/ )=-


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