Messages in this thread Patch in this message | | | From | Alban Bedel <> | Subject | [PATCH 1/2] MIPS: ath79: Fix the ar724x clock calculation | Date | Sun, 22 Nov 2015 13:03:04 +0100 |
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From: Weijie Gao <hackpascal@gmail.com>
According to the AR7242 datasheet section 2.8, AR724X CPUs use a 40MHz input clock as the REF_CLK instead of 5MHz.
The correct CPU PLL calculation procedure is as follows: CPU_PLL = (FB * REF_CLK) / REF_DIV / 2.
This patch is compatible with the current calculation procedure with default FB and REF_DIV values.
Tested on AR7240, AR7241 and AR7242.
Signed-off-by: Weijie Gao <hackpascal@gmail.com> Signed-off-by: Alban Bedel <albeu@free.fr> [albeu@free.fr: Fixed the commit log message] --- arch/mips/ath79/clock.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/mips/ath79/clock.c b/arch/mips/ath79/clock.c index eb5117c..ed28465 100644 --- a/arch/mips/ath79/clock.c +++ b/arch/mips/ath79/clock.c @@ -26,7 +26,7 @@ #include "common.h" #define AR71XX_BASE_FREQ 40000000 -#define AR724X_BASE_FREQ 5000000 +#define AR724X_BASE_FREQ 40000000 #define AR913X_BASE_FREQ 5000000 static struct clk *clks[3]; @@ -103,8 +103,8 @@ static void __init ar724x_clocks_init(void) div = ((pll >> AR724X_PLL_FB_SHIFT) & AR724X_PLL_FB_MASK); freq = div * ref_rate; - div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK); - freq *= div; + div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK) * 2; + freq /= div; cpu_rate = freq; -- 2.0.0
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