Messages in this thread | | | Date | Mon, 2 Nov 2015 19:57:09 +0000 | From | Will Deacon <> | Subject | Re: [PATCH 4/4] locking: Introduce smp_cond_acquire() |
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On Mon, Nov 02, 2015 at 11:17:17AM -0800, Linus Torvalds wrote: > On Mon, Nov 2, 2015 at 10:37 AM, Will Deacon <will.deacon@arm.com> wrote: > > On Mon, Nov 02, 2015 at 10:08:24AM -0800, Linus Torvalds wrote: > >> On Mon, Nov 2, 2015 at 5:29 AM, Peter Zijlstra <peterz@infradead.org> wrote: > >> > +#define smp_cond_acquire(cond) do { \ > >> > + while (!(cond)) \ > >> > + cpu_relax(); \ > >> > + smp_read_barrier_depends(); /* ctrl */ \ > >> > + smp_rmb(); /* ctrl + rmb := acquire */ \ > >> > +} while (0) > >> > >> This code makes absolutely no sense. > >> > >> smp_read_barrier_depends() is about a memory barrier where there is a > >> data dependency between two accesses. The "depends" is very much about > >> the data dependency, and very much about *nothing* else. > > > > Paul wasn't so sure, which I think is why smp_read_barrier_depends() > > is already used in, for example, READ_ONCE_CTRL: > > > > http://lkml.kernel.org/r/20151007154003.GJ3910@linux.vnet.ibm.com > > Quoting the alpha architecture manual is kind of pointless, when NO > OTHER ARCHITECTURE OUT THERE guararantees that whole "read + > conditional orders wrt subsequent writes" _either_. > > (Again, with the exception of x86, which has the sane "we honor causality") > > Alpha isn't special. And smp_read_barrier_depends() hasn't magically > become something new. > > If people think that control dependency needs a memory barrier on > alpha, then it damn well needs on on all other weakly ordered > architectuers too, afaik. > > Either that "you cannot finalize a write unless all conditionals it > depends on are finalized" is true or it is not. That argument has > *never* been about some architecture-specific memory ordering model, > as far as I know.
You can imagine a (horribly broken) value-speculating architecture that would permit this re-ordering, but then you'd have speculative stores and thin-air values, which Alpha doesn't have.
> As to READ_ONCE_CTRL - two wrongs don't make a right.
Sure, I just wanted to point out the precedence and related discussion.
> That smp_read_barrier_depends() there doesn't make any sense either. > > And finally, the alpha architecture manual actually does have the > notion of "Dependence Constraint" (5.6.1.7) that talks about writes > that depend on previous reads (where "depends" is explicitly spelled > out to be about conditionals, write data _or_ write address). They are > actually constrained on alpha too.
In which case, it looks like we can remove the smp_read_barrier_depends instances from all of the control-dependency macros, but I'll defer to Paul in case he has some further insight. I assume you're ok with this patch if the smp_read_barrier_depends() is removed?
> > In this case, control dependencies are only referring to READ -> WRITE > > ordering, so they are honoured by ARM and PowerPC. > > Do ARM and PPC actually guarantee the generic "previous reads always > order before subsequent writes"?
Only to *dependent* subsequent writes, but Peter's patch makes all subsequent writes dependent on cond, so I think that's the right way to achieve the ordering we want.
Will
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