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SubjectRe: [PATCH 5/5] clk: qcom: Add MSM8996 Multimedia Clock Controller (MMCC) driver
On 11/17, Stephen Boyd wrote:
> +static struct clk_alpha_pll mmpll0_early = {
> + .offset = 0x0,
> + .vco_table = mmpll_p_vco,
> + .num_vco = ARRAY_SIZE(mmpll_p_vco),
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "mmpll0_early",
> + .parent_names = (const char *[]){ "xo" },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_ops,
> + },
> +};
> +
> +static struct clk_alpha_pll_postdiv mmpll0 = {
> + .offset = 0x0,
> + .width = 4,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "mmpll0",
> + .parent_names = (const char *[]){ "mmpll0_early" },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_postdiv_ops,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_alpha_pll mmpll1_early = {
> + .offset = 0x30,
> + .vco_table = mmpll_p_vco,
> + .num_vco = ARRAY_SIZE(mmpll_p_vco),
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "mmpll1_early",
> + .parent_names = (const char *[]){ "xo" },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_ops,
> + },
> +};
> +
> +static struct clk_alpha_pll_postdiv mmpll1 = {
> + .offset = 0x30,
> + .width = 4,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "mmpll1",
> + .parent_names = (const char *[]){ "mmpll1_early" },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_postdiv_ops,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};

These are missing the .enable_reg and .enable_mask members to do
the proper FSM voting. I'll add that in v2.

--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project


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