Messages in this thread | | | Date | Tue, 10 Nov 2015 12:27:17 -0600 | Subject | Re: [RFC PATCH] tsc: synchronize TSCs on buggy Intel Xeon E5 CPUs with offset error | From | Josh Hunt <> |
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On Tue, Nov 10, 2015 at 12:24 PM, Josh Hunt <joshhunt00@gmail.com> wrote: > > On Mon, Nov 9, 2015 at 4:02 PM, Peter Zijlstra <peterz@infradead.org> wrote: >> >> On Mon, Nov 09, 2015 at 01:59:02PM -0600, gratian.crisan@ni.com wrote: >> >> > The Intel Xeon E5 processor family suffers from errata[1] BT81: >> >> > +#ifdef CONFIG_X86_TSC >> > + /* >> > + * Xeon E5 BT81 errata: TSC is not affected by warm reset. >> > + * The TSC registers for CPUs other than CPU0 are not cleared by a warm >> > + * reset resulting in a constant offset error. >> > + */ >> > + if ((c->x86 == 6) && (c->x86_model == 0x3f)) >> > + set_cpu_bug(c, X86_BUG_TSC_OFFSET); >> > +#endif >> >> That's hardly a family, that's just one, Haswell server. > > > Are you actually observing this problem on this processor? > > The document you've referenced and the x86_model # above do not match up. The errata should be for Intel processors with an x86_model value of 0x2d by my calculations: > > Model: 1101b > Extended Model: 0010b > > The calc from cpu_detect() is: > if (c->x86 >= 0x6) > c->x86_model += ((tfms >> 16) & 0xf) << 4; > > 0x3f is a different CPU. > -- > Josh
Resending, as gmail inserted html and lkml dropped the previous reply...
-- Josh
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