Messages in this thread | | | Date | Wed, 03 Sep 2014 17:06:30 -0700 | From | David Daney <> | Subject | Re: [PATCH 03/12] of: Add binding document for MIPS GIC |
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On 09/03/2014 04:53 PM, Andrew Bresticker wrote: > On Tue, Sep 2, 2014 at 5:50 PM, David Daney <ddaney.cavm@gmail.com> wrote: [...] >> >> Your comments don't really make sense to me in the context of my knowledge >> of the GIC. >> >> Of course all the CP0 timer and performance counter interrupts are per-CPU >> and routed directly to the corresponding CP0_Cause[IP7..IP2] bits. We are >> don't need to give them further consideration. >> >> >> Here is the scenario you should consider: >> >> o 16 CPU cores. >> o 1 GIC routing interrupts from external sources to the 16 CPUs. >> o 2 network controllers each with an interrupt line routed to the GIC. >> >> Q: What would the GIC "interrupts" property look like? >> >> Note that the GIC doesn't have a single "interrupt-parent", as it can route >> interrupts to *all* 16 CPUs. >> >> I propose that the GIC have neither an "interrupt-parent", nor "interrupts". >> The fact that it is an "mti,global-interrupt-controller", means that the >> software drivers for the GIC already know how to route interrupts, and any >> information the device tree could contain is redundant. > > Ok, I misunderstood your opposition to the binding. > > My intention for the "interrupt-parent" and "interrupts" property of > the GIC was to express that GIC interrupts are routed to the CPU > interrupt vectors and that a certain set of these vectors are > available for use by the GIC. I would agree that these are mostly > redundant (obviously the GIC routes interrupts to CPU interrupt > vecotrs) and that it is not the most accurate description of the > GIC-CPU relationship (the CPU interrupt controller are per-CPU, not > global, and the GIC can route interrupts to any of them), though I'm > not sure that there's a better way of describing it in DT. > > So that leaves us with something like this: > > interrupt-controller@1bdc0000 { > compatible = "mti,global-interrupt-controller"; > > interrupt-controller; > #interrupt-cells = <2>; > > available-cpu-vectors = <2>, <3>, ...
Exactly what I had in mind, except for the missing "reg" property.
This gives software the information it needs, but doesn't impose any policy.
I will defer to others on the exact name the "available-cpu-vectors" should have.
> }; > > DT folks, thoughts? > >
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