Messages in this thread | | | Date | Mon, 1 Sep 2014 15:52:31 +0200 | From | Peter Zijlstra <> | Subject | Re: [PATCH 5/5] perf, x86: Use Broadwell cache event list for Haswell |
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On Mon, Aug 25, 2014 at 03:43:31PM -0700, Andi Kleen wrote: > From: Andi Kleen <ak@linux.intel.com> > > Use the newly added Broadwell cache event list for Haswell too. > They are identical, but Haswell is very different from the Sandy Bridge > list that was used previously. That fixes a wide range of mis-counting > cache events. > > The node events are now only for retired memory events. > > The prefetch events are gone now. They way the hardware counts > them is very misleading (some prefetches included, others not), so > it seemed best to leave them out. > > Signed-off-by: Andi Kleen <ak@linux.intel.com> > --- > arch/x86/kernel/cpu/perf_event_intel.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c > index 53bd98d..190b29e 100644 > --- a/arch/x86/kernel/cpu/perf_event_intel.c > +++ b/arch/x86/kernel/cpu/perf_event_intel.c > @@ -2692,8 +2692,8 @@ __init int intel_pmu_init(void) > case 63: /* 22nm Haswell Server */ > case 69: /* 22nm Haswell ULT */ > x86_pmu.late_ack = true; > - memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, sizeof(hw_cache_event_ids)); > - memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); > + memcpy(hw_cache_event_ids, bdw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); > + memcpy(hw_cache_extra_regs, bdw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
We name things for the earliest chip they're valid for. This means this is inconsistent and 'wrong'. These tables should be called after haswell not broadwell.
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