Messages in this thread | | | Date | Fri, 1 Aug 2014 09:44:30 +0200 | From | Peter Zijlstra <> | Subject | Re: [PATCH 2/3] x86 perf: Protect LBR msrs accessing against potential #GP |
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On Fri, Aug 01, 2014 at 09:38:25AM +0200, Peter Zijlstra wrote: > On Thu, Jul 31, 2014 at 02:41:02AM -0700, kan.liang@intel.com wrote: > > From: Kan Liang <kan.liang@intel.com> > > > > Intel PT will take over LBR hardware. If RTIT_CTL.TraceEn=1, any attempt to > > read or write the LBR or LER MSRs, including LBR_TOS, will result in a #GP. > > Intel PT can be enabled/disabled at runtime by hardware/BIOS, so it's better > > LBR MSRs can be protected at runtime. > > > > The {rd,wr}msrl_goto can protect LBR accessing against the potential #GP. > > Furthermore, it will not impact the "fast" path's performance. > > NAK! > > I already said this isn't going to ever happen. > > Both PT and LBR are arbitrated through the kernel, therefore we can (and > must) deny PT when there's existing LBR usage and vice versa. > > We will not hijack resources like this full stop end of story. > > Fuck hardware/BIOS, they should _NOT_ be touching this. > > The 3 people in the world with access to an x86 hardware debugger had > better be competent and know WTF they're doing and the BIOS can just > piss off right now, they should not be touching this _EVER_.
I yelled at BIOS engineers over their PMU usage and $vendor added a BIOS knob to disable that, I'll yell at BIOS engineers again, just give me their number.
Really, say NO already. [unhandled content-type:application/pgp-signature] | |