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    Subject[PATCH 3.14 56/94] arm64: mm: Make icache synchronisation logic huge page aware
    Date
    3.14-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Steve Capper <steve.capper@linaro.org>

    commit 923b8f5044da753e4985ab15c1374ced2cdf616c upstream.

    The __sync_icache_dcache routine will only flush the dcache for the
    first page of a compound page, potentially leading to stale icache
    data residing further on in a hugetlb page.

    This patch addresses this issue by taking into consideration the
    order of the page when flushing the dcache.

    Reported-by: Mark Brown <broonie@linaro.org>
    Tested-by: Mark Brown <broonie@linaro.org>
    Signed-off-by: Steve Capper <steve.capper@linaro.org>
    Acked-by: Will Deacon <will.deacon@arm.com>
    Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

    ---
    arch/arm64/mm/flush.c | 3 ++-
    1 file changed, 2 insertions(+), 1 deletion(-)

    --- a/arch/arm64/mm/flush.c
    +++ b/arch/arm64/mm/flush.c
    @@ -79,7 +79,8 @@ void __sync_icache_dcache(pte_t pte, uns
    return;

    if (!test_and_set_bit(PG_dcache_clean, &page->flags)) {
    - __flush_dcache_area(page_address(page), PAGE_SIZE);
    + __flush_dcache_area(page_address(page),
    + PAGE_SIZE << compound_order(page));
    __flush_icache_all();
    } else if (icache_is_aivivt()) {
    __flush_icache_all();



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