Messages in this thread | | | Date | Tue, 22 Jul 2014 01:01:17 +0200 | From | Borislav Petkov <> | Subject | Re: [PATCH] x86, TSC: Add a software TSC offset |
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On Mon, Jul 21, 2014 at 03:43:36PM -0700, Andy Lutomirski wrote: > I have some reason to believe that this is almost an intentional bug > on the part of the BIOS vendor.
Hiding SMIs or some other dumb, I-know-how-to-do-stuff-better-than-you BIOS gunk.
> IIRC it was actually quite expensive, at least on Sandy Bridge.
Hmm, strange. So after the first fence and when you get to retire the second fence, you will have only the RDTSC eligible for retirement and everything that's coming behind it in program order can still go out-of-order. Unless the second fence flushes more stuff. I most likely am missing something.
> Maybe AMD is different. > > Anyway, if some future uarch breaks this, I could resurrect my old > hack: do a TSC-dependent load prior to returning. Loads are ordered, > and the hackish load can't be reordered wrt RDTSC due to > data-dependency, so we're in business :)
:-)
-- Regards/Gruss, Boris.
Sent from a fat crate under my desk. Formatting is fine. --
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