Messages in this thread | | | Date | Fri, 11 Jul 2014 10:08:55 -0700 | Subject | Re: [PATCH 01/13] clk: tegra: Add binding for the Tegra124 DFLL clocksource | From | Andrew Bresticker <> |
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On Fri, Jul 11, 2014 at 9:48 AM, Tuomas Tynkkynen <ttynkkynen@nvidia.com> wrote: > > > On 11/07/14 19:28, Andrew Bresticker wrote: >> >> On Thu, Jul 10, 2014 at 2:42 PM, Tuomas Tynkkynen <ttynkkynen@nvidia.com> >> wrote: >>> >>> The DFLL is the main clocksource for the fast CPU cluster on Tegra124 >>> and also provides automatic CPU rail voltage scaling as well. The DFLL >>> is a separate IP block from the usual Tegra124 clock-and-reset >>> controller, so it gets its own node in the device tree. >> >> >>> diff --git >>> a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt >>> b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt >> >> >>> +- nvidia,pmic-voltage-table: Array of 2-tuples. Each entry should have >>> the >>> + form <register-value voltage-in-uV>, indicating the register value >>> that >>> + needs to be programmed to the PMIC for changing the VDD_CPU voltage to >>> + the specified voltage. The table must be in ascending order by the >>> voltage. >> >> >> Instead of listing the register values for each voltage in the DT, >> can't you use regulator_list_voltage() to create this map? >> > > I don't see a way to get the register values that way, unless we assume that > the mapping is linear and doesn't have holes.
Hmm... I guess if you don't assume it's linear and continuous you'd have to iterate over all 256 selectors.
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