Messages in this thread | | | Subject | Re: [PATCH 0/4] New Qualcomm PMIC pin controller drivers | From | "Ivan T. Ivanov" <> | Date | Thu, 10 Jul 2014 16:39:18 +0300 |
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On Wed, 2014-07-09 at 07:02 -0700, Bjorn Andersson wrote: > On Wed, Jul 9, 2014 at 4:43 AM, Linus Walleij <linus.walleij@linaro.org> wrote: > > On Wed, Jul 9, 2014 at 1:13 PM, Ivan T. Ivanov <iivanov@mm-sol.com> wrote: > >> On Wed, 2014-07-09 at 11:43 +0200, Linus Walleij wrote: > >>> On Mon, Jul 7, 2014 at 5:11 PM, Ivan T. Ivanov <iivanov@mm-sol.com> wrote:
<snip>
> However, the device tree bindings are a different thing; as the > properties used to describe the hardware doesn't relate to how we > communicate with it I think we should be able to (and therefor should) > use the same documentation for the two (rather 7) chips.
Agreed.
> > >> Not sure. Björn patches cover older PMIC chips, if not mistaken, mine > >> cover PMIC's used with APQ8074 and onward [1]. Main difference is > >> the bus which connects them to SoC, interrupts handling, runtime > >> pin type detection and register map. > > > > Correct Ivan; we do however share the same issues related to how to do > interrupt handling,
Yep, but do we actually need to do interrupt handling in driver? Interrupts are handled by parent device. GPIO client drivers could use interrupt-controller registered by core driver?
> units for properties and how to split/reuse > between gpio and mpp. Also we have solved the pins vs groups vs > functions slightly different, that should all be aligned I think.
Sure.
<snip>
> > Then I guess even if the chips are totally unrelated it'd be interesting > > to have you two guys cross-review each other's drivers so the behaviour > > is consistent across qualcomm platforms. > > > > I hope we can meet somewhere in between
Sure.
Regards, Ivan
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