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    Subject[PATCH 3.14 084/228] clk: tegra: Fix wrong value written to PLLE_AUX
    Date
    3.14-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Tuomas Tynkkynen <ttynkkynen@nvidia.com>

    commit d2c834abe2b39a2d5a6c38ef44de87c97cbb34b4 upstream.

    The value written to PLLE_AUX was incorrect due to a wrong variable
    being used. Without this fix SATA does not work.

    Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
    Tested-by: Mikko Perttunen <mperttunen@nvidia.com>
    Reviewed-by: Thierry Reding <treding@nvidia.com>
    Tested-by: Thierry Reding <treding@nvidia.com>
    Acked-by: Thierry Reding <treding@nvidia.com>
    Signed-off-by: Mike Turquette <mturquette@linaro.org>
    [mturquette@linaro.org: improved changelog]
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

    ---
    drivers/clk/tegra/clk-pll.c | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    --- a/drivers/clk/tegra/clk-pll.c
    +++ b/drivers/clk/tegra/clk-pll.c
    @@ -1718,7 +1718,7 @@ struct clk *tegra_clk_register_plle_tegr
    "pll_re_vco");
    } else {
    val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
    - pll_writel(val, pll_params->aux_reg, pll);
    + pll_writel(val_aux, pll_params->aux_reg, pll);
    }

    clk = _tegra_clk_register_pll(pll, name, parent_name, flags,



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