Messages in this thread | | | Date | Mon, 26 May 2014 16:42:34 +0300 | From | Heikki Krogerus <> | Subject | Re: [PATCHv3 2/4] ACPI / LPSS: custom power domain for LPSS |
| |
On Mon, May 26, 2014 at 03:03:27PM +0200, Rafael J. Wysocki wrote: > On Friday, May 23, 2014 04:15:09 PM Heikki Krogerus wrote: > > A power domain where we save the context of the additional > > LPSS registers. We need to do this or all LPSS devices are > > left in reset state when resuming from D3 on some Baytrails. > > The devices with the fractional clock divider also have > > zeros for N and M values after resuming unless they are > > reset. > > > > Li Aubrey found the root cause for the issue. The idea of > > using power domain for LPSS came from Mika Westerberg. > > > > Reported-by: Jin Yao <yao.jin@linux.intel.com> > > Suggested-by: Li Aubrey <aubrey.li@linux.intel.com> > > Tested-by: Mika Westerberg <mika.westerberg@linux.intel.com> > > Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> > > Queued up for 3.16, but I needed to rebase it to take some other changes > into account. Can you please have a look and the bleeding-edge branch in > my tree and see if everything looks good in there?
I checked the bleeding-edge and it looks good to me. Thanks for taking care of the issue with "%lx".
About the sparse warning from the clk-fractional-divider.c. Since there is no real issue, let's follow the style in the other clock types and ignore the warning. So let's keep that patch as it is. OK?
-- heikki
| |